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intel: Modify BL31 address mapping
Hadi Asyrafi authored 
Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragmentation
Signed-off-by: default avatarHadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099
cf82aff0
Name Last commit Last update
..
allwinner Merge "allwinner: Fix incorrect ARISC code patch offset check" into integration
amlogic Merge changes from topic "amlogic-g12a" into integration
arm Merge "Use the proper size for tb_fw_cfg_dtb" into integration
common Add UBSAN support and handlers
hisilicon hikey: fix to load FIP by partition table.
imx imx: Fix multiple definition of ipc_handle
intel/soc intel: Modify BL31 address mapping
layerscape Enable -Wshadow always
marvell delay: timeout detection support
mediatek Merge "Enable -Wshadow always" into integration
nvidia/tegra Tegra194: smmu: add support for backup multiple smmu regs
qemu qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
renesas/rcar Enable -Wshadow always
rockchip rockchip: Prevent macro expansion in paths
rpi rpi4: Add stdout-path to device tree
socionext uniphier: set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver
st plat/st: Fix incorrect return value
ti/k3 ti: k3: common: Add PIE support
xilinx Enable -Wlogical-op always