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ROMLIB: Optimize memory layout when ROMLIB is used
Louis Mayencourt authored 
ROMLIB extract functions code from BL images to put them inside ROM.
This has for effect to reduce the size of the BL images.

This patch take this size reduction into consideration to optimize the
memory layout of BL2.
A new "PLAT_ARM_BL2_ROMLIB_OPTIMIZATION" macro is defined and used to
reduce "PLAT_ARM_MAX_BL2_SIZE". This allows to remove the gap between
BL1 and BL2 when ROMLIB is used and provides more room for BL31.

The current memory gain is 0x6000 for fvp and 0x8000 for juno.

Change-Id: I71c2c2c63b57bce5b22a125efaefc486ff3e87be
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
e7b39089
Name Last commit Last update
bl1 TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U
bl2 Refactor ARMv8.3 Pointer Authentication support code
bl2u TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U
bl31 Neoverse N1 Errata Workaround 1542419
bl32 AArch32: Disable Secure Cycle Counter
common FDT helper functions: Respect architecture in PSCI function IDs
docs doc: Misc syntax and spelling fixes
drivers gpio: stm32_gpio: do not mix error code types
fdts fdts: stm32mp1: move FDCAN to PLL4_R
include delay: correct timeout_init_us()
lib Merge "Neoverse N1 Errata Workaround 1542419" into integration
make_helpers Fix the CAS spinlock implementation
plat ROMLIB: Optimize memory layout when ROMLIB is used
services Merge changes from topic "jc/coverity-fixes" into integration
tools Remove RSA PKCS#1 v1.5 support from cert_tool
.checkpatch.conf Re-apply GIT_COMMIT_ID check for checkpatch
.editorconfig Add python configuration for editorconfig
.gitignore meson: Rename platform directory to amlogic
Makefile Fix the CAS spinlock implementation
dco.txt Drop requirement for CLA in contribution.md
license.rst doc: De-duplicate readme and license files
readme.rst doc: Formatting fixes for readme.rst
readme.rst

Trusted Firmware-A

Trusted Firmware-A (TF-A) is a reference implementation of secure world software for Arm A-Profile architectures (Armv8-A and Armv7-A), including an Exception Level 3 (EL3) Secure Monitor. It provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution states.

TF-A implements Arm interface standards, including:

The code is designed to be portable and reusable across hardware platforms and software models that are based on the Armv8-A and Armv7-A architectures.

In collaboration with interested parties, we will continue to enhance TF-A with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology.

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