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Add barriers to handle Secure Timer interrupts correctly
Achin Gupta authored 
This patch adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.

Change-Id: Ie2f01f4f2e5c032ba61c7014d09ad86a3c5a0b97
19623142
Name Last commit Last update
bl1 Merge pull request #170 from achingupta/ag/tf-issues#226
bl2 Call platform_is_primary_cpu() only from reset handler
bl31 Merge pull request #179 from jcastillo-arm/jc/tf-issues/219
bl32/tsp Add barriers to handle Secure Timer interrupts correctly
common Merge pull request #177 from jcastillo-arm/jc/tf-issues/096
docs Merge pull request #179 from jcastillo-arm/jc/tf-issues/219
drivers Merge pull request #177 from jcastillo-arm/jc/tf-issues/096
fdts Reserve some DDR DRAM for secure use on FVP platforms
include Add workarounds for selected Cortex-A57 r0p0 and Juno errata
lib Add workarounds for selected Cortex-A57 r0p0 and Juno errata
plat Juno: Add support for PSCI cpu_suspend api
services Merge pull request #178 from soby-mathew/sm/optmize_el3_context
tools/fip_create Improve BL3-0 documentation
.gitignore Update .gitignore
Makefile Rework the crash reporting in BL3-1 to use less stack
acknowledgements.md Build system: Fixes #2: Add multi-platform support
contributing.md Update contributing.md with new integration process
license.md Update year in copyright text to 2014
readme.md Trusted Firmware v0.4 release documentation