- 13 Sep, 2019 1 commit
-
-
Anusha Srivatsa authored
Add support for loading DMC v1.09 for Icelake. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 08 Jul, 2019 5 commits
-
-
Anusha Srivatsa authored
Add support for loading v33 of GuC on ICL. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for loading v33 of GuC on KBL. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for loading v33 of GuC on SKL. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for loading v33 of GuC on GLK. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for loading v33 of GuC on BXT. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 18 Apr, 2019 7 commits
-
-
Anusha Srivatsa authored
Add supoort for ICL HuC. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for guC v32.0.3 for ICL Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for HuC v03.01.2893 for GLK Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for guC v32.0.3 for GLK Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for guC v32.0.3 for KBL. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for guC v32.0.3 for SKL Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
Add support for guC v32.0.3 for BXT. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 28 Nov, 2018 1 commit
-
-
Anusha Srivatsa authored
Add support for v1.8.2893 for BXT huC. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 26 Sep, 2018 1 commit
-
-
Anusha Srivatsa authored
Add Support for Icelake DMC. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 02 Jan, 2018 1 commit
-
-
Anusha Srivatsa authored
This version includes since v1.06: 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 27 Nov, 2017 1 commit
-
-
Anusha Srivatsa authored
This update includes(since v1.26) Following additions from ver1.27 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 02 Nov, 2017 1 commit
-
-
Anusha Srivatsa authored
This update includes(since v1.01) 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 25 Oct, 2017 3 commits
-
-
Anusha Srivatsa authored
This update includes(since v9.14) 1. Aggressive DCC implementation for supported platforms. 2. Fixing Issue with Default Guc Log changes for OCA using special Control Bit Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
This update includes(since v8.7) 1. Fixing Issue with Default Guc Log changes for OCA using special Control Bit Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
This update includes(since v6.1) 1. Fixing Issue with Default Guc Log changes for OCA using special Control Bit Cc: Rodrigo vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 20 Oct, 2017 1 commit
-
-
Anusha Srivatsa authored
DMC provides additional graphics low-power idle states. It provides capability to save and restore display registers across these low-power states independently from the OS/Kernel This is the first release of DMC for Cannonlake. This major version will be just upgraded on code when it is required software changes for API/ABI compatibility. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 12 Oct, 2017 1 commit
-
-
Anusha Srivatsa authored
DMC provides additional graphics low-power idle states. It provides capability to save and restore display registers across these low-power states independently from the OS/Kernel This is the first release of DMC for Geminilake. This major version will be just upgraded on code when it is required software changes for API/ABI compatibility. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 24 Feb, 2017 1 commit
-
-
Rodrigo Vivi authored
For some reason these 2 files got corrupted when propagating the release to this repository. i915 firmware got first release at: https://01.org/linuxgraphics/downloads/firmware then propagated to linux-firmware.git. The version on 01.org are the right ones. This issue has been identified by Jason. He noticed that GuC image from linux-firmware.git wasn't getting loaded on his Kabylake, while the version on 01.org was working propertly. In a further review I identified that also GuC image for Broxton faced a similar issue. All other files on i915 are the proper one matching with the ones released on 01.org. Cc: Jason Curtiss <jason.curtiss@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
- 07 Feb, 2017 5 commits
-
-
Anusha Srivatsa authored
This update includes (since v8.12): 1. Sub-feature level control for power management features. 2. Clean-up for power management interface. 3. Bug Fix for multi context scheduler flag. 8.12 contained since v 5.1: 1. Add per engine preemption support to scheduler 2. Minor bug fixes 3. Add support to log media reset count Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
This update contains (since v7.6): 1. Update parameter name (interface change). 2. Fix for power impact issue. 7.6 contained since v 5.1: 1. Add per engine preemption support in scheduler. 2. Fix for Sleep Shared Area Pointer Validation. 3. Fix for Golden Context init for Render only for Engine Reset. 4. Fix for Forcewake Render check. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
This release is to support the following features: Gen95 HuC KBL BRC Kernel: - First release. Cc:Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
This release is to support the following features: Gen9 HuC BXT BRC Kernel: - Update SkipFrame to avoid conditional batch buffer issue in driver - Updated for open source driver - Fix overflow issue - Enable ME distortion based QP adjustment - Fix incorrect cost table loading when ME detection is enabled Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
Anusha Srivatsa authored
This release is to support the following features: Gen9 HuC AVC BRC Kernel: - Update SkipFrame to avoid conditional batch buffer issue in driver - Updated for open source driver - Fix overflow issue - Enable ME distortion based QP adjustment - Fix incorrect cost table loading when ME detection is enabled CC: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
-
- 11 Aug, 2016 1 commit
-
-
Rodrigo Vivi authored
1.26 is the stable and recommended firmware for Skylake. However one conflict in i915 accidentally restored 1.23 making that the default in some kernel out there. So, let's restore this 1.23 here. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97182 Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
- 01 Jul, 2016 3 commits
-
-
Rodrigo Vivi authored
i915 now loads the specific major/minor version of the firmware instead of loading the symbolic links. So this patch also removes symbolic links from the firmware components that never had the firmware loaded directly and let the symbolic links only for the cases where some versions of i915 might load the symbolic link while new versions loads the file directly. I considered making copies but this would increase this repository size in ~ 25%. The symbolic links now on shall never be updated. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
Rodrigo Vivi authored
This is the first version of the FW for KBL. Although we are stepping back from symbolic links, when kbl_dmc_ver1_01 was introduced there was the link so let's keep it around for a while. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
Rodrigo Vivi authored
Following additions from previous version 1. Updated FW to wait for all PLLs to turn on for complete power on. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
- 16 Mar, 2016 1 commit
-
-
Tom O'Rourke authored
This update contains: 1. Fix for engine reset issue of incorrectly decoding engine state address. 2. Fix scheduling issue where submit queue of an idle engine is not scheduled when another submit queue is full. 3. Reorganized SLPC interface. 4. Enabled IBC (intelligent bias control) for GT3 and GT4. The interface is changed. Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
- 10 Feb, 2016 1 commit
-
-
Rodrigo Vivi authored
Version: 1.26 Date : 02/01/2016 Notes: Following additions from ver1.26 1. WA for NV12 flicker issues. Fixed HTP for restore program Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
- 20 Oct, 2015 2 commits
-
-
Rodrigo Vivi authored
This versions has the risk of "DMC RAM corruption issue" fixed on 1.23. So let's remove old version and let only the latest one available for now. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
Rodrigo Vivi authored
Version: 1.23 Date : 10/19/2015 Notes: Following additions from ver1.22 1. WA for Palette and DMC RAM corruption issue. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.22 DC3_DC5_COUNT 80030 DC5_DC6_COUNT 8002C Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
- 23 Sep, 2015 2 commits
-
-
Rodrigo Vivi authored
The code points to the major version that is a link to the most recent one, so we can remove the old firmware blobs. For tests and validation purposes we will let few minor versions available, but we need to let linux-firmware repo as clean as possible, so let's remove old and unused ones. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
Rodrigo Vivi authored
Version: 1.22 Date : 9/23/2015 Notes: Following additions from ver1.21 1. PLL lock wait time updated 2. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.21 DC3_DC5_COUNT 80030 DC5_DC6_COUNT 8002C Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-
- 17 Sep, 2015 1 commit
-
-
Rodrigo Vivi authored
Following additions from previous version 1. Updated FW for NV12 enabling 2. Changes to the waits times for pll enable and disable. 3. Fixed GT interrupts issue 4. DC3_DC5_COUNT: 80038 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-