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Following additions from ver1.19
1. Changes to the waits times for pll enable and disable.
2. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.19
DC3_DC5_COUNT                  80030
DC5_DC6_COUNT                  8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Following additions:
  1. Updated FW for NV12 enabling
  3. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.18 and ver1.17
  DC3_DC5_COUNT                  80030
  DC5_DC6_COUNT                  8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Following additions:
1. The DE_RRMR and DE_GUCRMR register bits are set before the restore of
the registers to mask the flip done, etc. Once all the registers are
restored, these registers are restored.
2. The pipe interrupt registers are restored only after the plane has
been enabled.
3. Naming of the file changed from .5 to .16 to make it two decimal
points for increased number of versions that can be supported.
4. DC 5 and 6 count locations are in the below mentioned offsets
DC3_DC5_COUNT                  80030
DC5_DC6_COUNT                  8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>