soc_info: Introduce SRAM size

At the moment we assume the SPL load size to be limited to 32KB, even
though many SoCs have more SRAM A1 or a large SRAM C directly after SRAM
A1.

To later allow to extend the SPL load size, let's introduce a SoC
specific variable to hold the SRAM size after the SPL load address. This
could either cover the whole of SRAM A1, or even SRAM C, if that is
contiguous to SRAM A1.

Eventually this variable is meant to hold the *usable* SRAM size, so not
including regions that are used by the BROM code. However this value is
very SoC specific and not documented, and the SPL size is limited by the
thunk and stack buffers anyway at the moment, so the values used here
right now are just taken from the respective manuals.
Signed-off-by: Andre Przywara <osp@andrep.de>

soc_info.c

@@ -158,6 +158,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 48 * 1024,
 		.needs_l2en   = true,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_a10_compat,
@@ -167,6 +168,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 48 * 1024,
 		.needs_l2en   = true,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_a10_compat,
@@ -176,6 +178,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 48 * 1024,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_a10_compat,
 	},{
@@ -184,6 +187,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0x46E00, .thunk_size = 0x200,
 		.swap_buffers = ar100_abusing_sram_swap_buffers,
+		.sram_size    = 64 * 1024,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_h3_compat,
 	},{
@@ -192,6 +196,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0x22E00, .thunk_size = 0x200,
 		.swap_buffers = a31_sram_swap_buffers,
+		.sram_size    = 32 * 1024,
 		.watchdog     = &wd_h3_compat,
 	},{
 		.soc_id       = 0x1667, /* Allwinner A33, R16 */
@@ -199,6 +204,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0x46E00, .thunk_size = 0x200,
 		.swap_buffers = ar100_abusing_sram_swap_buffers,
+		.sram_size    = 32 * 1024,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_h3_compat,
 	},{
@@ -208,6 +214,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x11000,
 		.thunk_addr   = 0x1A200, .thunk_size = 0x200,
 		.swap_buffers = a64_sram_swap_buffers,
+		.sram_size    = 192 * 1024,
 		.sid_base     = 0x01C14000,
 		.sid_offset   = 0x200,
 		.rvbar_reg    = 0x017000A0,
@@ -221,6 +228,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x11000,
 		.thunk_addr   = 0x23400, .thunk_size = 0x200,
 		.swap_buffers = a80_sram_swap_buffers,
+		.sram_size    = 40 * 1024,
 		.sid_base     = 0X01C0E000,
 		.sid_offset   = 0x200,
 		.watchdog     = &wd_a80,
@@ -231,6 +239,7 @@ soc_info_t soc_info_table[] = {
 		.mmu_tt_addr  = 0x44000,
 		.thunk_addr   = 0x46E00, .thunk_size = 0x200,
 		.swap_buffers = ar100_abusing_sram_swap_buffers,
+		.sram_size    = 32 * 1024,
 		.sid_base     = 0x01C14000,
 		.sid_offset   = 0x200,
 		.watchdog     = &wd_h3_compat,
@@ -241,6 +250,7 @@ soc_info_t soc_info_table[] = {
 		.mmu_tt_addr  = 0x8000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 108 * 1024,
 		.sid_base     = 0x01C14000,
 		.sid_offset   = 0x200,
 		.sid_fix      = true,
@@ -254,6 +264,7 @@ soc_info_t soc_info_table[] = {
 		.mmu_tt_addr  = 0x8000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 60 * 1024,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_h3_compat,
 	},{
@@ -263,6 +274,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x11000,
 		.thunk_addr   = 0x1A200, .thunk_size = 0x200,
 		.swap_buffers = a64_sram_swap_buffers,
+		.sram_size    = 144 * 1024,
 		.sid_base     = 0x01C14000,
 		.sid_offset   = 0x200,
 		.rvbar_reg    = 0x017000A0,
@@ -275,6 +287,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 48 * 1024,
 		.sid_base     = 0x01C1B000,
 		.sid_offset   = 0x200,
 		.watchdog     = &wd_a10_compat,
@@ -285,6 +298,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x21000,
 		.thunk_addr   = 0x2A200, .thunk_size = 0x200,
 		.swap_buffers = h6_sram_swap_buffers,
+		.sram_size    = 152 * 1024,
 		.sid_base     = 0x03006000,
 		.sid_offset   = 0x200,
 		.rvbar_reg    = 0x09010040,
@@ -298,6 +312,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x21000,
 		.thunk_addr   = 0x2A200, .thunk_size = 0x200,
 		.swap_buffers = v831_sram_swap_buffers,
+		.sram_size    = 228 * 1024,
 		.sid_base     = 0x03006000,
 		.sid_offset   = 0x200,
 		.watchdog     = &wd_h6_compat,
@@ -308,6 +323,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x21000,
 		.thunk_addr   = 0x2A200, .thunk_size = 0x200,
 		.swap_buffers = h616_sram_swap_buffers,
+		.sram_size    = 224 * 1024,
 		.sid_base     = 0x03006000,
 		.sid_offset   = 0x200,
 		.rvbar_reg    = 0x09010040,

soc_info.h

@@ -115,6 +115,7 @@ typedef struct {
 	bool               sid_fix;      /* Use SID workaround (read via register) */
 	/* Use SMC workaround (enter secure mode) if can't read from this address */
 	uint32_t           needs_smc_workaround_if_zero_word_at_addr;
+	uint32_t           sram_size;	/* Usable contiguous SRAM at spl_addr */
 	sram_swap_buffers *swap_buffers;
 } soc_info_t;