Commit 3c2faa16 authored by Icenowy Zheng's avatar Icenowy Zheng
Browse files

uart0-helloworld-sdboot: add support for V831 SoC



V831 SoC is one of sun8i family (with Cortex-A7 CPUs), and it follows a
similar memory map with H6.

Add support for it. The detection for H6-style memory map is positive on
V831, because it have the same version of GIC at the same address.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
parent c6111193
...@@ -144,6 +144,7 @@ enum sunxi_gpio_number { ...@@ -144,6 +144,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPH_UART0 (2) #define SUN6I_GPH_UART0 (2)
#define SUN8I_H3_GPA_UART0 (2) #define SUN8I_H3_GPA_UART0 (2)
#define SUN8I_V3S_GPB_UART0 (3) #define SUN8I_V3S_GPB_UART0 (3)
#define SUN8I_V831_GPH_UART0 (5)
#define SUN50I_H5_GPA_UART0 (2) #define SUN50I_H5_GPA_UART0 (2)
#define SUN50I_H6_GPH_UART0 (2) #define SUN50I_H6_GPH_UART0 (2)
#define SUN50I_A64_GPB_UART0 (4) #define SUN50I_A64_GPB_UART0 (4)
...@@ -307,6 +308,7 @@ void soc_detection_init(void) ...@@ -307,6 +308,7 @@ void soc_detection_init(void)
#define soc_is_h6() (soc_id == 0x1728) #define soc_is_h6() (soc_id == 0x1728)
#define soc_is_r40() (soc_id == 0x1701) #define soc_is_r40() (soc_id == 0x1701)
#define soc_is_v3s() (soc_id == 0x1681) #define soc_is_v3s() (soc_id == 0x1681)
#define soc_is_v831() (soc_id == 0x1817)
/* A10s and A13 share the same ID, so we need a little more effort on those */ /* A10s and A13 share the same ID, so we need a little more effort on those */
...@@ -382,7 +384,7 @@ void clock_init_uart_h6(void) ...@@ -382,7 +384,7 @@ void clock_init_uart_h6(void)
void clock_init_uart(void) void clock_init_uart(void)
{ {
if (soc_is_h6()) if (soc_is_h6() || soc_is_v831())
clock_init_uart_h6(); clock_init_uart_h6();
else else
clock_init_uart_legacy(); clock_init_uart_legacy();
...@@ -436,6 +438,10 @@ void gpio_init(void) ...@@ -436,6 +438,10 @@ void gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
} else if (soc_is_v831()) {
sunxi_gpio_set_cfgpin(SUNXI_GPH(9), SUN8I_V831_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(10), SUN8I_V831_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(10), SUNXI_GPIO_PULL_UP);
} else { } else {
/* Unknown SoC */ /* Unknown SoC */
while (1) {} while (1) {}
...@@ -512,7 +518,7 @@ int get_boot_device(void) ...@@ -512,7 +518,7 @@ int get_boot_device(void)
u32 *spl_signature = (void *)0x4; u32 *spl_signature = (void *)0x4;
if (soc_is_a64() || soc_is_a80() || soc_is_h5()) if (soc_is_a64() || soc_is_a80() || soc_is_h5())
spl_signature = (void *)0x10004; spl_signature = (void *)0x10004;
if (soc_is_h6()) if (soc_is_h6() || soc_is_v831())
spl_signature = (void *)0x20004; spl_signature = (void *)0x20004;
/* Check the eGON.BT0 magic in the SPL header */ /* Check the eGON.BT0 magic in the SPL header */
...@@ -530,7 +536,7 @@ int get_boot_device(void) ...@@ -530,7 +536,7 @@ int get_boot_device(void)
void bases_init(void) void bases_init(void)
{ {
if (soc_is_h6()) { if (soc_is_h6() || soc_is_v831()) {
pio_base = H6_PIO_BASE; pio_base = H6_PIO_BASE;
uart0_base = H6_UART0_BASE; uart0_base = H6_UART0_BASE;
} else { } else {
...@@ -571,6 +577,8 @@ int main(void) ...@@ -571,6 +577,8 @@ int main(void)
uart0_puts("Allwinner R40!\n"); uart0_puts("Allwinner R40!\n");
else if (soc_is_v3s()) else if (soc_is_v3s())
uart0_puts("Allwinner V3s!\n"); uart0_puts("Allwinner V3s!\n");
else if (soc_is_v831())
uart0_puts("Allwinner V831!\n");
else else
uart0_puts("unknown Allwinner SoC!\n"); uart0_puts("unknown Allwinner SoC!\n");
......
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