Commit 47b611cc authored by Andre Przywara's avatar Andre Przywara
Browse files

spi: Add support for R40



The R40 is closely related to the A20, but has in fact a newer
generation SPI controller.
Add the R40 SoC ID to the right places to enable SPI support.

Tested on a Bananapi M2 Berry with SPI flash attached to header pins.
Signed-off-by: default avatarAndre Przywara <osp@andrep.de>
parent 14ff3e36
...@@ -136,6 +136,7 @@ static uint32_t spi_base(feldev_handle *dev) ...@@ -136,6 +136,7 @@ static uint32_t spi_base(feldev_handle *dev)
case 0x1623: /* A10 */ case 0x1623: /* A10 */
case 0x1625: /* A13 */ case 0x1625: /* A13 */
case 0x1651: /* A20 */ case 0x1651: /* A20 */
case 0x1701: /* R40 */
return 0x01C05000; return 0x01C05000;
case 0x1817: /* V831 */ case 0x1817: /* V831 */
return 0x05010000; return 0x05010000;
...@@ -209,6 +210,7 @@ static bool spi0_init(feldev_handle *dev) ...@@ -209,6 +210,7 @@ static bool spi0_init(feldev_handle *dev)
break; break;
case 0x1623: /* Allwinner A10 */ case 0x1623: /* Allwinner A10 */
case 0x1651: /* Allwinner A20 */ case 0x1651: /* Allwinner A20 */
case 0x1701: /* Allwinner R40 */
gpio_set_cfgpin(dev, PC, 0, SUNXI_GPC_SPI0); gpio_set_cfgpin(dev, PC, 0, SUNXI_GPC_SPI0);
gpio_set_cfgpin(dev, PC, 1, SUNXI_GPC_SPI0); gpio_set_cfgpin(dev, PC, 1, SUNXI_GPC_SPI0);
gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0); gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0);
......
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