spi: Add A20 pinmux configuration

A20 (as does A10) uses pins 0,1,2 and 23 in bank C
for SPI 0.
Signed-off-by: Priit Laes <priit.laes@paf.com>

fel-spiflash.c

@@ -160,6 +160,12 @@ static bool spi0_init(feldev_handle *dev)
 		gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0);
 		gpio_set_cfgpin(dev, PC, 3, SUNXI_GPC_SPI0);
 		break;
+	case 0x1651: /* Allwinner A20 */
+		gpio_set_cfgpin(dev, PC, 0, SUNXI_GPC_SPI0);
+		gpio_set_cfgpin(dev, PC, 1, SUNXI_GPC_SPI0);
+		gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0);
+		gpio_set_cfgpin(dev, PC, 23, SUNXI_GPC_SPI0);
+		break;
 	case 0x1689: /* Allwinner A64 */
 		gpio_set_cfgpin(dev, PC, 0, SUN50I_GPC_SPI0);
 		gpio_set_cfgpin(dev, PC, 1, SUN50I_GPC_SPI0);