Commit ada24830 authored by Andre Przywara's avatar Andre Przywara
Browse files

fel: A64/H5: Allow bigger SPL size



The A64 and H5 have a rather generous SRAM C directly adjacent to
SRAM A1, so we can make use of the larger continuous SRAM area to
increase the maximum SPL size.

Move the location of the FEL stack backup buffer up, towards the end of
SRAM C. We restrict ourselves to the slightly tighter requirements of
the H5, to be able to still share the joint swap_buffers data structure.
Signed-off-by: default avatarAndre Przywara <osp@andrep.de>
parent 2f59b574
...@@ -60,16 +60,18 @@ sram_swap_buffers a31_sram_swap_buffers[] = { ...@@ -60,16 +60,18 @@ sram_swap_buffers a31_sram_swap_buffers[] = {
/* /*
* A64 has 32KiB of SRAM A at 0x10000 and a large SRAM C at 0x18000. SRAM A * A64 has 32KiB of SRAM A at 0x10000 and a large SRAM C at 0x18000. SRAM A
* and SRAM C reside in the address space back-to-back without any gaps, thus * and SRAM C reside in the address space back-to-back without any gaps, thus
* representing a singe large contiguous area. Everything is the same as on * representing a singe large contiguous area. The BROM FEL code memory areas
* A10/A13/A20, but just shifted by 0x10000. * are the same as on A10/A13/A20, but just shifted by 0x10000.
* We put the backup buffers towards the end of SRAM C, in a location that
* is also available on the H5.
*/ */
sram_swap_buffers a64_sram_swap_buffers[] = { sram_swap_buffers a64_sram_swap_buffers[] = {
/* 0x11C00-0x11FFF (IRQ stack) */ /* 0x11C00-0x11FFF (IRQ stack) */
{ .buf1 = 0x11C00, .buf2 = 0x1A400, .size = 0x0400 }, { .buf1 = 0x11C00, .buf2 = 0x31400, .size = 0x0400 },
/* 0x15C00-0x16FFF (Stack) */ /* 0x15C00-0x16FFF (Stack) */
{ .buf1 = 0x15C00, .buf2 = 0x1A800, .size = 0x1400 }, { .buf1 = 0x15C00, .buf2 = 0x31800, .size = 0x1400 },
/* 0x17C00-0x17FFF (Something important) */ /* 0x17C00-0x17FFF (Something important) */
{ .buf1 = 0x17C00, .buf2 = 0x1BC00, .size = 0x0400 }, { .buf1 = 0x17C00, .buf2 = 0x32c00, .size = 0x0400 },
{ .size = 0 } /* End of the table */ { .size = 0 } /* End of the table */
}; };
...@@ -212,9 +214,9 @@ soc_info_t soc_info_table[] = { ...@@ -212,9 +214,9 @@ soc_info_t soc_info_table[] = {
.name = "A64", .name = "A64",
.spl_addr = 0x10000, .spl_addr = 0x10000,
.scratch_addr = 0x11000, .scratch_addr = 0x11000,
.thunk_addr = 0x1A200, .thunk_size = 0x200, .thunk_addr = 0x31200, .thunk_size = 0x200,
.swap_buffers = a64_sram_swap_buffers, .swap_buffers = a64_sram_swap_buffers,
.sram_size = 192 * 1024, .sram_size = 140 * 1024,
.sid_base = 0x01C14000, .sid_base = 0x01C14000,
.sid_offset = 0x200, .sid_offset = 0x200,
.rvbar_reg = 0x017000A0, .rvbar_reg = 0x017000A0,
...@@ -272,9 +274,9 @@ soc_info_t soc_info_table[] = { ...@@ -272,9 +274,9 @@ soc_info_t soc_info_table[] = {
.name = "H5", .name = "H5",
.spl_addr = 0x10000, .spl_addr = 0x10000,
.scratch_addr = 0x11000, .scratch_addr = 0x11000,
.thunk_addr = 0x1A200, .thunk_size = 0x200, .thunk_addr = 0x31200, .thunk_size = 0x200,
.swap_buffers = a64_sram_swap_buffers, .swap_buffers = a64_sram_swap_buffers,
.sram_size = 144 * 1024, .sram_size = 140 * 1024,
.sid_base = 0x01C14000, .sid_base = 0x01C14000,
.sid_offset = 0x200, .sid_offset = 0x200,
.rvbar_reg = 0x017000A0, .rvbar_reg = 0x017000A0,
......
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