meminfo: fix 'dram_clk' reporting for frequencies that are not multiples of 24

The K and M factors encode values 1-4 in two bits (starting from 1
and not 0). The typical DRAM clock frequency setup uses K=2 and M=2,
which means that both of them are read as 1 from the bit fields.
That's why a10-meminfo used to work in most cases (1/1 is the same
as 2/2). However a10-meminfo happens to report wrong 'dram_clk' if
the other values of K and M are selected. This patch fixes it.

a10-meminfo.c

@@ -256,8 +256,8 @@ int main(int argc, char **argv)
      */
      p.clock = (24 *
          ((ccm->pll5_cfg >> CCM_PLL5_FACTOR_N) & CCM_PLL5_FACTOR_N_SIZE) *
-         ((ccm->pll5_cfg >> CCM_PLL5_FACTOR_K) & CCM_PLL5_FACTOR_K_SIZE) /
-         ((ccm->pll5_cfg >> CCM_PLL5_FACTOR_M) & CCM_PLL5_FACTOR_M_SIZE)
+         (((ccm->pll5_cfg >> CCM_PLL5_FACTOR_K) & CCM_PLL5_FACTOR_K_SIZE) + 1) /
+         (((ccm->pll5_cfg >> CCM_PLL5_FACTOR_M) & CCM_PLL5_FACTOR_M_SIZE) + 1)
     );
 
     /* Print dram_para struct */