fel: Disable MMU to get more SRAM space and fix A13 problems
The FEL BROM code has the MMU enabled for some reason (while I-cache and D-cache are disabled). Most likely the intention was to get a somewhat better performance. Everything is mapped as TEXCB=00000 (strongly ordered), except for the 0x00000000 (SRAM) and 0xFFF00000 (BROM) sections, which are mapped as TEXCB=00100 (normal uncached memory). This becomes a problem for the A13 SoC, because it has less SRAM than the other chips. A13 stores the MMU addresses translation table at 0x8000 and uses up 16 KiB of the SRAM space there (while the A10, A20 and A31s keep the MMU table in the secure SRAM at 0x20000). And because the 'spl' command needs space for backing up the FEL stacks, it was clashing with the MMU table. The solution is simple. We just backup the addresses translation table and disable the MMU before running the SPL. And then restore it back to the original state. This fixes problems on A13. Re-enabling the MMU in the end is only necessary to avoid performance losses. For example, the transfer speed of the 'fel write' command on A20 would drop from ~320 KB/s to ~260 KB/s without MMU. Signed-off-by:Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by:
Hans de Goede <hdegoede@redhat.com>
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