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(Changing to a proper struct initializer avoids a possible
compiler warning.)
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>

Since we lack enough information to get parameters.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Triggered by command line arguments.
Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

And bail if it fails to match anything we support.
Signed-off-by: Luc Verhaegen <libv@skynet.be>

No functional changes.
Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

Now we write out a dram file for u-boot directly.
Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

* rename a10-meminfo to meminfo
* add static build to Makefile
* fix operand warning
* built binary verified on proper linux and android
Signed-off-by: Luc Verhaegen <libv@skynet.be>

The K and M factors encode values 1-4 in two bits (starting from 1
and not 0). The typical DRAM clock frequency setup uses K=2 and M=2,
which means that both of them are read as 1 from the bit fields.
That's why a10-meminfo used to work in most cases (1/1 is the same
as 2/2). However a10-meminfo happens to report wrong 'dram_clk' if
the other values of K and M are selected. This patch fixes it.

Get it from the dllcr registers instead of always returning 0.

PLL1_tun2 had a wrong comment (0x34) in the original and was swapped to
accomidate this position. Actually the comment was wrong and the
location right, so this patch puts pll1_tun2 to 0x38.
0x34 is now reserved.

DDR runs from the PLL5 and has several option to be configured, just as
factor N, M, P and K. This patch probes all those registers to determine
the clock.