1. 06 Nov, 2017 2 commits
    • Maxime Ripard's avatar
      fel: Check the U-Boot's CRC instead of its size · e753821e
      Maxime Ripard authored
      
      
      The current code checks that the transferred size is matching the size
      reported in the image header.
      
      Unfortunately, the transferred image might be padded, which doesn't change
      anything at the functional level, but will make that check trigger since
      the actual image will be smaller than the transferred data.
      
      Change that logic to first check that the transferred size isn't less that
      the header image size, which will still be an error, and then check for the
      CRC of the image itself. This will prove to be an more robust integrity
      check than what we have right now anyway.
      
      The CRC used in the image header is the CRC32 algorithm, that is
      implemented in the zlib, which is installed on most devices on the planet,
      so we can just use that implementation instead of rolling our own.
      Tested-by: default avatarFrank Kunz <mailinglists@kunz-im-inter.net>
      Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
      e753821e
    • Maxime Ripard's avatar
      fel: Use U-Boot's header structure · b1bbc431
      Maxime Ripard authored
      
      
      The U-Boot image parsing code so far has been relying on hardcoded offsets
      directly into the image's buffer.
      
      While that works, it's a bit obscure and isn't practical to understand and
      modify.
      
      Let's add the structure definition, and convert the code to use it.
      Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
      b1bbc431
  2. 15 Aug, 2017 1 commit
  3. 29 Apr, 2017 1 commit
    • Icenowy Zheng's avatar
      fel: enable support for v2 SPL · c8ada384
      Icenowy Zheng authored
      
      
      The version 2 of SPL added the possibility to add a device tree name in
      the header, with adding some pad and using a reserved word.
      
      As FEL boot currently doesn't need the device tree name, directly raise
      the maximum supported version number to 2.
      Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
      c8ada384
  4. 31 Mar, 2017 1 commit
  5. 28 Feb, 2017 2 commits
    • Siarhei Siamashka's avatar
      fel: Enable the SMC workaround for H3/H5/A64/H64 · 275827ad
      Siarhei Siamashka authored
      
      
      Use a hardwired L.NOP instruction from the OpenRISC reset
      vector as a way to check if the workaround is necessary.
      Because these L.NOP instructions are guaranteed to be there
      and are read-only, this is the most reliable non-invasive test.
      
      Reading SID would be less reliable because it is one-time
      programmable and theoretically may be set to zero on some boards.
      Signed-off-by: default avatarSiarhei Siamashka <siarhei.siamashka@gmail.com>
      275827ad
    • Andre Przywara's avatar
      fel: SMC workaround to enter "secure boot" FEL mode on some SoCs · 8c45b33e
      Andre Przywara authored
      
      
      If an SoC has the "secure boot" fuse burned, it will enter FEL mode in
      non-secure state, so with the SCR.NS bit set. Since in this mode the
      secure/non-secure state restrictions are actually observed, we suffer
      from several restrictions:
      - No access to the SID information (both via memory mapped and "register").
      - No access to secure SRAM (SRAM A2 on H3/A64/H5).
      - No access to the secure side of the GIC, so it can't be configured to
        be accessible from non-secure world.
      - No RMR trigger on ARMv8 cores to bring the core into AArch64.
      Those limitations make a board pretty useless for many applications.
      
      However it has been found out that a simple "smc" call will immediately
      return from monitor mode, but with the NS bit cleared, so access to all
      secure peripherals is suddenly possible.
      
      Add all the necessary support code for doing a runtime check and
      activating this workaround. Affected SoCs need to have the "smc"
      workaround enabled in their soc_info struct.
      Signed-off-by: default avatarAndre Przywara <osp@andrep.de>
      ["sunxi-fel smc" command changed to automatic detection by Siarhei]
      Signed-off-by: default avatarSiarhei Siamashka <siarhei.siamashka@gmail.com>
      8c45b33e
  6. 13 Feb, 2017 1 commit
  7. 11 Feb, 2017 4 commits
  8. 03 Feb, 2017 1 commit
  9. 27 Jan, 2017 5 commits
  10. 21 Jan, 2017 1 commit
  11. 30 Dec, 2016 1 commit
  12. 28 Dec, 2016 13 commits
  13. 21 Dec, 2016 1 commit
  14. 13 Dec, 2016 2 commits
  15. 07 Dec, 2016 2 commits
  16. 01 Dec, 2016 2 commits