Skip to content

GitLab

Switch branch/tag
Find file Normal viewHistoryPermalink
cortex_a53.S 2.94 KB
Newer Older
Yatharth Kochar's avatar
AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor    
Yatharth Kochar committed
1
2
3 
/*
 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
 *
dp-arm's avatar
Use SPDX license identifiers    
dp-arm committed
4 
 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kochar's avatar
AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor    
Yatharth Kochar committed
5
6
7
8
9
10
11
12
13
14
15
16
17 
 */
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <cortex_a53.h>
#include <cpu_macros.S>
#include <debug.h>

	/* ---------------------------------------------
	 * Disable intra-cluster coherency
	 * ---------------------------------------------
	 */
func cortex_a53_disable_smp
Varun Wadekar's avatar
Unique names for defines in the CPU libraries    
Varun Wadekar committed
18
19
20 
	ldcopr16	r0, r1, CORTEX_A53_ECTLR
	bic64_imm	r0, r1, CORTEX_A53_ECTLR_SMP_BIT
	stcopr16	r0, r1, CORTEX_A53_ECTLR
Yatharth Kochar's avatar
AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor    
Yatharth Kochar committed
21
22
23
24
25
26
27
28
29
30
31
32
33
34 
	isb
	dsb	sy
	bx	lr
endfunc cortex_a53_disable_smp

	/* -------------------------------------------------
	 * The CPU Ops reset function for Cortex-A53.
	 * -------------------------------------------------
	 */
func cortex_a53_reset_func
	/* ---------------------------------------------
	 * Enable the SMP bit.
	 * ---------------------------------------------
	 */
Varun Wadekar's avatar
Unique names for defines in the CPU libraries    
Varun Wadekar committed
35
36
37 
	ldcopr16	r0, r1, CORTEX_A53_ECTLR
	orr64_imm	r0, r1, CORTEX_A53_ECTLR_SMP_BIT
	stcopr16	r0, r1,	CORTEX_A53_ECTLR
Yatharth Kochar's avatar
AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor    
Yatharth Kochar committed
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117 
	isb
	bx	lr
endfunc cortex_a53_reset_func

	/* ----------------------------------------------------
	 * The CPU Ops core power down function for Cortex-A53.
	 * ----------------------------------------------------
	 */
func cortex_a53_core_pwr_dwn
	push	{r12, lr}

	/* Assert if cache is enabled */
#if ASM_ASSERTION
	ldcopr	r0, SCTLR
	tst	r0, #SCTLR_C_BIT
	ASM_ASSERT(eq)
#endif

	/* ---------------------------------------------
	 * Flush L1 caches.
	 * ---------------------------------------------
	 */
	mov	r0, #DC_OP_CISW
	bl	dcsw_op_level1

	/* ---------------------------------------------
	 * Come out of intra cluster coherency
	 * ---------------------------------------------
	 */
	pop	{r12, lr}
	b	cortex_a53_disable_smp
endfunc cortex_a53_core_pwr_dwn

	/* -------------------------------------------------------
	 * The CPU Ops cluster power down function for Cortex-A53.
	 * Clobbers: r0-r3
	 * -------------------------------------------------------
	 */
func cortex_a53_cluster_pwr_dwn
	push	{r12, lr}

	/* Assert if cache is enabled */
#if ASM_ASSERTION
	ldcopr	r0, SCTLR
	tst	r0, #SCTLR_C_BIT
	ASM_ASSERT(eq)
#endif

	/* ---------------------------------------------
	 * Flush L1 caches.
	 * ---------------------------------------------
	 */
	mov	r0, #DC_OP_CISW
	bl	dcsw_op_level1

	/* ---------------------------------------------
	 * Disable the optional ACP.
	 * ---------------------------------------------
	 */
	bl	plat_disable_acp

	/* ---------------------------------------------
	 * Flush L2 caches.
	 * ---------------------------------------------
	 */
	mov	r0, #DC_OP_CISW
	bl	dcsw_op_level2

	/* ---------------------------------------------
	 * Come out of intra cluster coherency
	 * ---------------------------------------------
	 */
	pop	{r12, lr}
	b	cortex_a53_disable_smp
endfunc cortex_a53_cluster_pwr_dwn

declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
	cortex_a53_reset_func, \
	cortex_a53_core_pwr_dwn, \
	cortex_a53_cluster_pwr_dwn