• Soby Mathew's avatar
    PSCI: Introduce new platform interface to describe topology · 82dcc039
    Soby Mathew authored
    This patch removes the assumption in the current PSCI implementation that MPIDR
    based affinity levels map directly to levels in a power domain tree. This
    enables PSCI generic code to support complex power domain topologies as
    envisaged by PSCIv1.0 specification. The platform interface for querying
    the power domain topology has been changed such that:
    
    1. The generic PSCI code does not generate MPIDRs and use them to query the
       platform about the number of power domains at a particular power level. The
       platform now provides a description of the power domain tree on the SoC
       through a data structure. The existing platform APIs to provide the same
       information have been removed.
    
    2. The linear indices returned by plat_core_pos_by_mpidr() and
       plat_my_core_pos() are used to retrieve core power domain nodes from the
       power domain tree. Power domains above the core level are accessed using a
       'parent' field in the tree node descriptors.
    
    The platform describes the power domain tree in an array of 'unsigned
    char's. The first entry in the array specifies the number of power domains at
    the highest power level implemented in the system. Each susbsequent entry
    corresponds to a power domain and contains the number of power domains that are
    its direct children. This array is exported to the generic PSCI implementation
    via the new `plat_get_power_domain_tree_desc()` platform API.
    
    The PSCI generic code uses this array to populate its internal power domain tree
    using the Breadth First Search like algorithm. The tree is split into two
    arrays:
    
    1. An array that contains all the core power domain nodes
    
    2. An array that contains all the other power domain nodes
    
    A separate array for core nodes allows certain core specific optimisations to
    be implemented e.g. remove the bakery lock, re-use per-cpu data framework for
    storing some information.
    
    Entries in the core power domain array are allocated such that the
    array index of the domain is equal to the linear index returned by
    plat_core_pos_by_mpidr() and plat_my_core_pos() for the MPIDR
    corresponding to that domain. This relationship is key to be able to use
    an MPIDR to find the corresponding core power domain node, traverse to higher
    power domain nodes and index into arrays that contain core specific
    information.
    
    An introductory document has been added to briefly describe the new interface.
    
    Change-Id: I4b444719e8e927ba391cae48a23558308447da13
    82dcc039
psci_common.c 18.3 KB