Commit 28abb2c2 authored by Deepika Bhavnani's avatar Deepika Bhavnani Committed by Soby Mathew
Browse files

hisilicon: Unify Platform specific defines for PSCI module



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: default avatarDeepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I327a8a2ab0f0e49bd62f413296c3b326393422b6
parent 90b686cf
/* /*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -28,13 +28,13 @@ ...@@ -28,13 +28,13 @@
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
#define PLATFORM_CACHE_LINE_SIZE 64 #define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT 2 #define PLATFORM_CLUSTER_COUNT U(2)
#define PLATFORM_CORE_COUNT_PER_CLUSTER 4 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER) PLATFORM_CORE_COUNT_PER_CLUSTER)
#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
PLATFORM_CLUSTER_COUNT + 1) PLATFORM_CLUSTER_COUNT + U(1))
#define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE U(2) #define PLAT_MAX_OFF_STATE U(2)
......
/* /*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -25,12 +25,12 @@ ...@@ -25,12 +25,12 @@
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
#define PLATFORM_CACHE_LINE_SIZE 64 #define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT 2 #define PLATFORM_CLUSTER_COUNT U(2)
#define PLATFORM_CORE_COUNT_PER_CLUSTER 4 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER) PLATFORM_CORE_COUNT_PER_CLUSTER)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
PLATFORM_CLUSTER_COUNT + 1) PLATFORM_CLUSTER_COUNT + 1)
#define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_RET_STATE U(1)
......
/* /*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -34,9 +34,9 @@ ...@@ -34,9 +34,9 @@
#define BOOT_EMMC_NAME "l-loader.bin" #define BOOT_EMMC_NAME "l-loader.bin"
#define PLATFORM_CACHE_LINE_SIZE (64) #define PLATFORM_CACHE_LINE_SIZE (64)
#define PLATFORM_CLUSTER_COUNT (1) #define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CORE_COUNT (4) #define PLATFORM_CORE_COUNT U(4)
#define PLATFORM_MAX_CPUS_PER_CLUSTER (4) #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
/* IO framework user */ /* IO framework user */
#define MAX_IO_DEVICES (4) #define MAX_IO_DEVICES (4)
......
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