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Unverified Commit 37cdad2a authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
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Merge pull request #1821 from Yann-lms/stm32mp1_2019-02-14 

Series of new patches for STM32MP1
parents 83321666 6c1e71e1
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drivers/st/clk/stm32mp1_clk.c
View file @ 37cdad2a
/* /*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/ */
...@@ -18,25 +18,27 @@ ...@@ -18,25 +18,27 @@
#include <common/debug.h> #include <common/debug.h>
#include <drivers/delay_timer.h> #include <drivers/delay_timer.h>
#include <drivers/generic_delay_timer.h> #include <drivers/generic_delay_timer.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <drivers/st/stm32mp1_clk.h> #include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_clkfunc.h> #include <drivers/st/stm32mp1_clkfunc.h>
#include <drivers/st/stm32mp1_rcc.h> #include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h> #include <dt-bindings/clock/stm32mp1-clksrc.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/spinlock.h>
#include <lib/utils_def.h> #include <lib/utils_def.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#define MAX_HSI_HZ 64000000 #define MAX_HSI_HZ 64000000
#define USB_PHY_48_MHZ 48000000
#define TIMEOUT_200MS (plat_get_syscnt_freq2() / 5U) #define TIMEOUT_US_200MS U(200000)
#define TIMEOUT_1S plat_get_syscnt_freq2() #define TIMEOUT_US_1S U(1000000)
#define PLLRDY_TIMEOUT TIMEOUT_200MS #define PLLRDY_TIMEOUT TIMEOUT_US_200MS
#define CLKSRC_TIMEOUT TIMEOUT_200MS #define CLKSRC_TIMEOUT TIMEOUT_US_200MS
#define CLKDIV_TIMEOUT TIMEOUT_200MS #define CLKDIV_TIMEOUT TIMEOUT_US_200MS
#define HSIDIV_TIMEOUT TIMEOUT_200MS #define HSIDIV_TIMEOUT TIMEOUT_US_200MS
#define OSCRDY_TIMEOUT TIMEOUT_1S #define OSCRDY_TIMEOUT TIMEOUT_US_1S
enum stm32mp1_parent_id { enum stm32mp1_parent_id {
/* Oscillators are defined in enum stm32mp_osc_id */ /* Oscillators are defined in enum stm32mp_osc_id */
...@@ -68,12 +70,20 @@ enum stm32mp1_parent_id { ...@@ -68,12 +70,20 @@ enum stm32mp1_parent_id {
_HCLK2, _HCLK2,
_CK_PER, _CK_PER,
_CK_MPU, _CK_MPU,
_USB_PHY_48,
_PARENT_NB, _PARENT_NB,
_UNKNOWN_ID = 0xff, _UNKNOWN_ID = 0xff,
}; };
/* Lists only the parent clock we are interested in */
enum stm32mp1_parent_sel { enum stm32mp1_parent_sel {
_I2C12_SEL,
_I2C35_SEL,
_STGEN_SEL,
_I2C46_SEL, _I2C46_SEL,
_SPI6_SEL,
_USART1_SEL,
_RNG1_SEL,
_UART6_SEL, _UART6_SEL,
_UART24_SEL, _UART24_SEL,
_UART35_SEL, _UART35_SEL,
...@@ -82,9 +92,9 @@ enum stm32mp1_parent_sel { ...@@ -82,9 +92,9 @@ enum stm32mp1_parent_sel {
_SDMMC3_SEL, _SDMMC3_SEL,
_QSPI_SEL, _QSPI_SEL,
_FMC_SEL, _FMC_SEL,
_ASS_SEL,
_USBPHY_SEL, _USBPHY_SEL,
_USBO_SEL, _USBO_SEL,
_STGEN_SEL,
_PARENT_SEL_NB, _PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff, _UNKNOWN_SEL = 0xff,
}; };
...@@ -164,9 +174,8 @@ struct stm32mp1_clk_gate { ...@@ -164,9 +174,8 @@ struct stm32mp1_clk_gate {
uint8_t bit; uint8_t bit;
uint8_t index; uint8_t index;
uint8_t set_clr; uint8_t set_clr;
enum stm32mp1_parent_sel sel; uint8_t sel; /* Relates to enum stm32mp1_parent_sel */
enum stm32mp1_parent_id fixed; uint8_t fixed; /* Relates to enum stm32mp1_parent_id */
bool secure;
}; };
struct stm32mp1_clk_sel { struct stm32mp1_clk_sel {
...@@ -189,21 +198,8 @@ struct stm32mp1_clk_pll { ...@@ -189,21 +198,8 @@ struct stm32mp1_clk_pll {
enum stm32mp_osc_id refclk[REFCLK_SIZE]; enum stm32mp_osc_id refclk[REFCLK_SIZE];
}; };
struct stm32mp1_clk_data { /* Clocks with selectable source and non set/clr register access */
const struct stm32mp1_clk_gate *gate; #define _CLK_SELEC(off, b, idx, s) \
const struct stm32mp1_clk_sel *sel;
const struct stm32mp1_clk_pll *pll;
const int nb_gate;
};
struct stm32mp1_clk_priv {
uint32_t base;
const struct stm32mp1_clk_data *data;
unsigned long osc[NB_OSC];
uint32_t pkcs_usb_value;
};
#define STM32MP1_CLK(off, b, idx, s) \
{ \ { \
.offset = (off), \ .offset = (off), \
.bit = (b), \ .bit = (b), \
...@@ -211,10 +207,10 @@ struct stm32mp1_clk_priv { ...@@ -211,10 +207,10 @@ struct stm32mp1_clk_priv {
.set_clr = 0, \ .set_clr = 0, \
.sel = (s), \ .sel = (s), \
.fixed = _UNKNOWN_ID, \ .fixed = _UNKNOWN_ID, \
.secure = 0, \
} }
#define STM32MP1_CLK_F(off, b, idx, f) \ /* Clocks with fixed source and non set/clr register access */
#define _CLK_FIXED(off, b, idx, f) \
{ \ { \
.offset = (off), \ .offset = (off), \
.bit = (b), \ .bit = (b), \
...@@ -222,10 +218,10 @@ struct stm32mp1_clk_priv { ...@@ -222,10 +218,10 @@ struct stm32mp1_clk_priv {
.set_clr = 0, \ .set_clr = 0, \
.sel = _UNKNOWN_SEL, \ .sel = _UNKNOWN_SEL, \
.fixed = (f), \ .fixed = (f), \
.secure = 0, \
} }
#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ /* Clocks with selectable source and set/clr register access */
#define _CLK_SC_SELEC(off, b, idx, s) \
{ \ { \
.offset = (off), \ .offset = (off), \
.bit = (b), \ .bit = (b), \
...@@ -233,10 +229,10 @@ struct stm32mp1_clk_priv { ...@@ -233,10 +229,10 @@ struct stm32mp1_clk_priv {
.set_clr = 1, \ .set_clr = 1, \
.sel = (s), \ .sel = (s), \
.fixed = _UNKNOWN_ID, \ .fixed = _UNKNOWN_ID, \
.secure = 0, \
} }
#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ /* Clocks with fixed source and set/clr register access */
#define _CLK_SC_FIXED(off, b, idx, f) \
{ \ { \
.offset = (off), \ .offset = (off), \
.bit = (b), \ .bit = (b), \
...@@ -244,32 +240,20 @@ struct stm32mp1_clk_priv { ...@@ -244,32 +240,20 @@ struct stm32mp1_clk_priv {
.set_clr = 1, \ .set_clr = 1, \
.sel = _UNKNOWN_SEL, \ .sel = _UNKNOWN_SEL, \
.fixed = (f), \ .fixed = (f), \
.secure = 0, \
} }
#define STM32MP1_CLK_SEC_SET_CLR(off, b, idx, s) \ #define _CLK_PARENT(idx, off, s, m, p) \
{ \
.offset = (off), \
.bit = (b), \
.index = (idx), \
.set_clr = 1, \
.sel = (s), \
.fixed = _UNKNOWN_ID, \
.secure = 1, \
}
#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
[(idx)] = { \ [(idx)] = { \
.offset = (off), \ .offset = (off), \
.src = (s), \ .src = (s), \
.msk = (m), \ .msk = (m), \
.parent = (p), \ .parent = (p), \
.nb_parent = ARRAY_SIZE((p)) \ .nb_parent = ARRAY_SIZE(p) \
} }
#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, \ #define _CLK_PLL(idx, type, off1, off2, off3, \
off4, off5, off6, \ off4, off5, off6, \
p1, p2, p3, p4) \ p1, p2, p3, p4) \
[(idx)] = { \ [(idx)] = { \
.plltype = (type), \ .plltype = (type), \
.rckxselr = (off1), \ .rckxselr = (off1), \
...@@ -285,113 +269,176 @@ struct stm32mp1_clk_priv { ...@@ -285,113 +269,176 @@ struct stm32mp1_clk_priv {
} }
static const uint8_t stm32mp1_clks[][2] = { static const uint8_t stm32mp1_clks[][2] = {
{CK_PER, _CK_PER}, { CK_PER, _CK_PER },
{CK_MPU, _CK_MPU}, { CK_MPU, _CK_MPU },
{CK_AXI, _ACLK}, { CK_AXI, _ACLK },
{CK_HSE, _HSE}, { CK_HSE, _HSE },
{CK_CSI, _CSI}, { CK_CSI, _CSI },
{CK_LSI, _LSI}, { CK_LSI, _LSI },
{CK_LSE, _LSE}, { CK_LSE, _LSE },
{CK_HSI, _HSI}, { CK_HSI, _HSI },
{CK_HSE_DIV2, _HSE_KER_DIV2}, { CK_HSE_DIV2, _HSE_KER_DIV2 },
}; };
#define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK),
STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK),
STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK),
STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
_CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
_CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
_CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 11, TZC1, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 12, TZC2, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
_CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _USART1_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 5, HASH1, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _CSI_KER), _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
_CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
_CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
_CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5),
_CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5),
_CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5),
_CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL),
_CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5),
_CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
_CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
_CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
_CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
_CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
_CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
};
static const uint8_t i2c12_parents[] = {
_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
};
static const uint8_t i2c35_parents[] = {
_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
};
static const uint8_t stgen_parents[] = {
_HSI_KER, _HSE_KER
}; };
static const uint8_t i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; static const uint8_t i2c46_parents[] = {
static const uint8_t uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER
_HSE_KER}; };
static const uint8_t uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
_HSE_KER}; static const uint8_t spi6_parents[] = {
static const uint8_t uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q
_HSE_KER}; };
static const uint8_t uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
_HSE_KER}; static const uint8_t usart1_parents[] = {
static const uint8_t sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER
static const uint8_t sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; };
static const uint8_t qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
static const uint8_t fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; static const uint8_t rng1_parents[] = {
static const uint8_t usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; _CSI, _PLL4_R, _LSE, _LSI
static const uint8_t usbo_parents[] = {_PLL4_R, _USB_PHY_48}; };
static const uint8_t stgen_parents[] = {_HSI_KER, _HSE_KER};
static const uint8_t uart6_parents[] = {
_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
};
static const uint8_t uart234578_parents[] = {
_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
};
static const uint8_t sdmmc12_parents[] = {
_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER
};
static const uint8_t sdmmc3_parents[] = {
_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER
};
static const uint8_t qspi_parents[] = {
_ACLK, _PLL3_R, _PLL4_P, _CK_PER
};
static const uint8_t fmc_parents[] = {
_ACLK, _PLL3_R, _PLL4_P, _CK_PER
};
static const uint8_t ass_parents[] = {
_HSI, _HSE, _PLL2
};
static const uint8_t usbphy_parents[] = {
_HSE_KER, _PLL4_R, _HSE_KER_DIV2
};
static const uint8_t usbo_parents[] = {
_PLL4_R, _USB_PHY_48
};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), _CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), _CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
uart24_parents), _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents),
uart35_parents), _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents),
STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents),
uart78_parents), _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents),
sdmmc12_parents), _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents),
STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents),
sdmmc3_parents), _CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, sdmmc12_parents),
STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), _CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, sdmmc3_parents),
STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), _CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), _CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), _CLK_PARENT(_ASS_SEL, RCC_ASSCKSELR, 0, 0x3, ass_parents),
STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), _CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
}; };
/* Define characteristic of PLL according type */ /* Define characteristic of PLL according type */
...@@ -413,26 +460,26 @@ static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { ...@@ -413,26 +460,26 @@ static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
static const uint8_t pllncfgr2[_DIV_NB] = { static const uint8_t pllncfgr2[_DIV_NB] = {
[_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
[_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
[_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT,
}; };
static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
STM32MP1_CLK_PLL(_PLL1, PLL_1600, _CLK_PLL(_PLL1, PLL_1600,
RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
_HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
STM32MP1_CLK_PLL(_PLL2, PLL_1600, _CLK_PLL(_PLL2, PLL_1600,
RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
_HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
STM32MP1_CLK_PLL(_PLL3, PLL_800, _CLK_PLL(_PLL3, PLL_800,
RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
_HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID),
STM32MP1_CLK_PLL(_PLL4, PLL_800, _CLK_PLL(_PLL4, PLL_800,
RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
_HSI, _HSE, _CSI, _I2S_CKIN), _HSI, _HSE, _CSI, _I2S_CKIN),
}; };
/* Prescaler table lookups for clock computation */ /* Prescaler table lookups for clock computation */
...@@ -449,33 +496,84 @@ static const uint8_t stm32mp1_axi_div[8] = { ...@@ -449,33 +496,84 @@ static const uint8_t stm32mp1_axi_div[8] = {
1, 2, 3, 4, 4, 4, 4, 4 1, 2, 3, 4, 4, 4, 4, 4
}; };
static const struct stm32mp1_clk_data stm32mp1_data = { /* RCC clock device driver private */
.gate = stm32mp1_clk_gate, static unsigned long stm32mp1_osc[NB_OSC];
.sel = stm32mp1_clk_sel, static struct spinlock reg_lock;
.pll = stm32mp1_clk_pll, static unsigned int gate_refcounts[NB_GATES];
.nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), static struct spinlock refcount_lock;
};
static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx)
{
return &stm32mp1_clk_gate[idx];
}
static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx)
{
return &stm32mp1_clk_sel[idx];
}
static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx)
{
return &stm32mp1_clk_pll[idx];
}
static int stm32mp1_lock_available(void)
{
/* The spinlocks are used only when MMU is enabled */
return (read_sctlr() & SCTLR_M_BIT) && (read_sctlr() & SCTLR_C_BIT);
}
static void stm32mp1_clk_lock(struct spinlock *lock)
{
if (stm32mp1_lock_available() == 0U) {
return;
}
/* Assume interrupts are masked */
spin_lock(lock);
}
static void stm32mp1_clk_unlock(struct spinlock *lock)
{
if (stm32mp1_lock_available() == 0U) {
return;
}
spin_unlock(lock);
}
bool stm32mp1_rcc_is_secure(void)
{
uintptr_t rcc_base = stm32mp_rcc_base();
static struct stm32mp1_clk_priv stm32mp1_clk_priv_data; return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0;
}
static unsigned long stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, void stm32mp1_clk_rcc_regs_lock(void)
enum stm32mp_osc_id idx) {
stm32mp1_clk_lock(&reg_lock);
}
void stm32mp1_clk_rcc_regs_unlock(void)
{
stm32mp1_clk_unlock(&reg_lock);
}
static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)
{ {
if (idx >= NB_OSC) { if (idx >= NB_OSC) {
return 0; return 0;
} }
return priv->osc[idx]; return stm32mp1_osc[idx];
} }
static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) static int stm32mp1_clk_get_gated_id(unsigned long id)
{ {
const struct stm32mp1_clk_gate *gate = priv->data->gate; unsigned int i;
int i;
int nb_clks = priv->data->nb_gate;
for (i = 0; i < nb_clks; i++) { for (i = 0U; i < NB_GATES; i++) {
if (gate[i].index == id) { if (gate_ref(i)->index == id) {
return i; return i;
} }
} }
...@@ -485,77 +583,64 @@ static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) ...@@ -485,77 +583,64 @@ static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
return -EINVAL; return -EINVAL;
} }
static enum stm32mp1_parent_sel static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i)
stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, int i)
{ {
const struct stm32mp1_clk_gate *gate = priv->data->gate; return (enum stm32mp1_parent_sel)(gate_ref(i)->sel);
return gate[i].sel;
} }
static enum stm32mp1_parent_id static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i)
stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, int i)
{ {
const struct stm32mp1_clk_gate *gate = priv->data->gate; return (enum stm32mp1_parent_id)(gate_ref(i)->fixed);
return gate[i].fixed;
} }
static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, static int stm32mp1_clk_get_parent(unsigned long id)
unsigned long id)
{ {
const struct stm32mp1_clk_sel *sel = priv->data->sel; const struct stm32mp1_clk_sel *sel;
uint32_t j, p_sel; uint32_t j, p_sel;
int i; int i;
enum stm32mp1_parent_id p; enum stm32mp1_parent_id p;
enum stm32mp1_parent_sel s; enum stm32mp1_parent_sel s;
uintptr_t rcc_base = stm32mp_rcc_base();
for (j = 0; j < ARRAY_SIZE(stm32mp1_clks); j++) { for (j = 0U; j < ARRAY_SIZE(stm32mp1_clks); j++) {
if (stm32mp1_clks[j][0] == id) { if (stm32mp1_clks[j][0] == id) {
return (int)stm32mp1_clks[j][1]; return (int)stm32mp1_clks[j][1];
} }
} }
i = stm32mp1_clk_get_id(priv, id); i = stm32mp1_clk_get_gated_id(id);
if (i < 0) { if (i < 0) {
return i; panic();
} }
p = stm32mp1_clk_get_fixed_parent(priv, i); p = stm32mp1_clk_get_fixed_parent(i);
if (p < _PARENT_NB) { if (p < _PARENT_NB) {
return (int)p; return (int)p;
} }
s = stm32mp1_clk_get_sel(priv, i); s = stm32mp1_clk_get_sel(i);
if (s >= _PARENT_SEL_NB) { if (s == _UNKNOWN_SEL) {
return -EINVAL; return -EINVAL;
} }
if (s >= _PARENT_SEL_NB) {
p_sel = (mmio_read_32(priv->base + sel[s].offset) >> sel[s].src) & panic();
sel[s].msk;
if (p_sel < sel[s].nb_parent) {
return (int)sel[s].parent[p_sel];
} }
ERROR("%s: no parents defined for clk id %ld\n", __func__, id); sel = clk_sel_ref(s);
p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & sel->msk;
if (p_sel < sel->nb_parent) {
return (int)sel->parent[p_sel];
}
return -EINVAL; return -EINVAL;
} }
static unsigned long stm32mp1_pll_get_fref_ck(struct stm32mp1_clk_priv *priv, static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll)
enum stm32mp1_pll_id pll_id)
{ {
const struct stm32mp1_clk_pll *pll = priv->data->pll; uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr);
uint32_t selr, src; uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK;
unsigned long refclk;
selr = mmio_read_32(priv->base + pll[pll_id].rckxselr);
src = selr & RCC_SELR_REFCLK_SRC_MASK;
refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); return stm32mp1_clk_get_fixed(pll->refclk[src]);
return refclk;
} }
/* /*
...@@ -564,20 +649,19 @@ static unsigned long stm32mp1_pll_get_fref_ck(struct stm32mp1_clk_priv *priv, ...@@ -564,20 +649,19 @@ static unsigned long stm32mp1_pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
* - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
* => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
*/ */
static unsigned long stm32mp1_pll_get_fvco(struct stm32mp1_clk_priv *priv, static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll)
enum stm32mp1_pll_id pll_id)
{ {
const struct stm32mp1_clk_pll *pll = priv->data->pll;
unsigned long refclk, fvco; unsigned long refclk, fvco;
uint32_t cfgr1, fracr, divm, divn; uint32_t cfgr1, fracr, divm, divn;
uintptr_t rcc_base = stm32mp_rcc_base();
cfgr1 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr1); cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);
fracr = mmio_read_32(priv->base + pll[pll_id].pllxfracr); fracr = mmio_read_32(rcc_base + pll->pllxfracr);
divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
refclk = stm32mp1_pll_get_fref_ck(priv, pll_id); refclk = stm32mp1_pll_get_fref(pll);
/* /*
* With FRACV : * With FRACV :
...@@ -586,13 +670,13 @@ static unsigned long stm32mp1_pll_get_fvco(struct stm32mp1_clk_priv *priv, ...@@ -586,13 +670,13 @@ static unsigned long stm32mp1_pll_get_fvco(struct stm32mp1_clk_priv *priv,
* Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
*/ */
if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
>> RCC_PLLNFRACR_FRACV_SHIFT; RCC_PLLNFRACR_FRACV_SHIFT;
unsigned long long numerator, denominator; unsigned long long numerator, denominator;
numerator = ((unsigned long long)divn + 1U) << 13; numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
numerator = (refclk * numerator) + fracv; numerator = refclk * numerator;
denominator = ((unsigned long long)divm + 1U) << 13; denominator = ((unsigned long long)divm + 1U) << 13;
fvco = (unsigned long)(numerator / denominator); fvco = (unsigned long)(numerator / denominator);
} else { } else {
fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U));
...@@ -601,11 +685,10 @@ static unsigned long stm32mp1_pll_get_fvco(struct stm32mp1_clk_priv *priv, ...@@ -601,11 +685,10 @@ static unsigned long stm32mp1_pll_get_fvco(struct stm32mp1_clk_priv *priv,
return fvco; return fvco;
} }
static unsigned long stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,
enum stm32mp1_pll_id pll_id,
enum stm32mp1_div_id div_id) enum stm32mp1_div_id div_id)
{ {
const struct stm32mp1_clk_pll *pll = priv->data->pll; const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
unsigned long dfout; unsigned long dfout;
uint32_t cfgr2, divy; uint32_t cfgr2, divy;
...@@ -613,42 +696,42 @@ static unsigned long stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, ...@@ -613,42 +696,42 @@ static unsigned long stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
return 0; return 0;
} }
cfgr2 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr2); cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2);
divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
dfout = stm32mp1_pll_get_fvco(priv, pll_id) / (divy + 1U); dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U);
return dfout; return dfout;
} }
static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) static unsigned long get_clock_rate(int p)
{ {
uint32_t reg, clkdiv; uint32_t reg, clkdiv;
unsigned long clock = 0; unsigned long clock = 0;
uintptr_t rcc_base = stm32mp_rcc_base();
switch (p) { switch (p) {
case _CK_MPU: case _CK_MPU:
/* MPU sub system */ /* MPU sub system */
reg = mmio_read_32(priv->base + RCC_MPCKSELR); reg = mmio_read_32(rcc_base + RCC_MPCKSELR);
switch (reg & RCC_SELR_SRC_MASK) { switch (reg & RCC_SELR_SRC_MASK) {
case RCC_MPCKSELR_HSI: case RCC_MPCKSELR_HSI:
clock = stm32mp1_clk_get_fixed(priv, _HSI); clock = stm32mp1_clk_get_fixed(_HSI);
break; break;
case RCC_MPCKSELR_HSE: case RCC_MPCKSELR_HSE:
clock = stm32mp1_clk_get_fixed(priv, _HSE); clock = stm32mp1_clk_get_fixed(_HSE);
break; break;
case RCC_MPCKSELR_PLL: case RCC_MPCKSELR_PLL:
clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
break; break;
case RCC_MPCKSELR_PLL_MPUDIV: case RCC_MPCKSELR_PLL_MPUDIV:
clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
reg = mmio_read_32(priv->base + RCC_MPCKDIVR); reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
clkdiv = reg & RCC_MPUDIV_MASK; clkdiv = reg & RCC_MPUDIV_MASK;
if (clkdiv != 0U) { if (clkdiv != 0U) {
clock /= stm32mp1_mpu_div[clkdiv]; clock /= stm32mp1_mpu_div[clkdiv];
} }
break; break;
default: default:
break; break;
...@@ -660,32 +743,32 @@ static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) ...@@ -660,32 +743,32 @@ static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
case _HCLK6: case _HCLK6:
case _PCLK4: case _PCLK4:
case _PCLK5: case _PCLK5:
reg = mmio_read_32(priv->base + RCC_ASSCKSELR); reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);
switch (reg & RCC_SELR_SRC_MASK) { switch (reg & RCC_SELR_SRC_MASK) {
case RCC_ASSCKSELR_HSI: case RCC_ASSCKSELR_HSI:
clock = stm32mp1_clk_get_fixed(priv, _HSI); clock = stm32mp1_clk_get_fixed(_HSI);
break; break;
case RCC_ASSCKSELR_HSE: case RCC_ASSCKSELR_HSE:
clock = stm32mp1_clk_get_fixed(priv, _HSE); clock = stm32mp1_clk_get_fixed(_HSE);
break; break;
case RCC_ASSCKSELR_PLL: case RCC_ASSCKSELR_PLL:
clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
break; break;
default: default:
break; break;
} }
/* System clock divider */ /* System clock divider */
reg = mmio_read_32(priv->base + RCC_AXIDIVR); reg = mmio_read_32(rcc_base + RCC_AXIDIVR);
clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
switch (p) { switch (p) {
case _PCLK4: case _PCLK4:
reg = mmio_read_32(priv->base + RCC_APB4DIVR); reg = mmio_read_32(rcc_base + RCC_APB4DIVR);
clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
break; break;
case _PCLK5: case _PCLK5:
reg = mmio_read_32(priv->base + RCC_APB5DIVR); reg = mmio_read_32(rcc_base + RCC_APB5DIVR);
clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
break; break;
default: default:
...@@ -693,16 +776,16 @@ static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) ...@@ -693,16 +776,16 @@ static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
} }
break; break;
case _CK_PER: case _CK_PER:
reg = mmio_read_32(priv->base + RCC_CPERCKSELR); reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);
switch (reg & RCC_SELR_SRC_MASK) { switch (reg & RCC_SELR_SRC_MASK) {
case RCC_CPERCKSELR_HSI: case RCC_CPERCKSELR_HSI:
clock = stm32mp1_clk_get_fixed(priv, _HSI); clock = stm32mp1_clk_get_fixed(_HSI);
break; break;
case RCC_CPERCKSELR_HSE: case RCC_CPERCKSELR_HSE:
clock = stm32mp1_clk_get_fixed(priv, _HSE); clock = stm32mp1_clk_get_fixed(_HSE);
break; break;
case RCC_CPERCKSELR_CSI: case RCC_CPERCKSELR_CSI:
clock = stm32mp1_clk_get_fixed(priv, _CSI); clock = stm32mp1_clk_get_fixed(_CSI);
break; break;
default: default:
break; break;
...@@ -710,65 +793,65 @@ static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) ...@@ -710,65 +793,65 @@ static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
break; break;
case _HSI: case _HSI:
case _HSI_KER: case _HSI_KER:
clock = stm32mp1_clk_get_fixed(priv, _HSI); clock = stm32mp1_clk_get_fixed(_HSI);
break; break;
case _CSI: case _CSI:
case _CSI_KER: case _CSI_KER:
clock = stm32mp1_clk_get_fixed(priv, _CSI); clock = stm32mp1_clk_get_fixed(_CSI);
break; break;
case _HSE: case _HSE:
case _HSE_KER: case _HSE_KER:
clock = stm32mp1_clk_get_fixed(priv, _HSE); clock = stm32mp1_clk_get_fixed(_HSE);
break; break;
case _HSE_KER_DIV2: case _HSE_KER_DIV2:
clock = stm32mp1_clk_get_fixed(priv, _HSE) >> 1; clock = stm32mp1_clk_get_fixed(_HSE) >> 1;
break; break;
case _LSI: case _LSI:
clock = stm32mp1_clk_get_fixed(priv, _LSI); clock = stm32mp1_clk_get_fixed(_LSI);
break; break;
case _LSE: case _LSE:
clock = stm32mp1_clk_get_fixed(priv, _LSE); clock = stm32mp1_clk_get_fixed(_LSE);
break; break;
/* PLL */ /* PLL */
case _PLL1_P: case _PLL1_P:
clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
break; break;
case _PLL1_Q: case _PLL1_Q:
clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_Q); clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q);
break; break;
case _PLL1_R: case _PLL1_R:
clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_R); clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R);
break; break;
case _PLL2_P: case _PLL2_P:
clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
break; break;
case _PLL2_Q: case _PLL2_Q:
clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_Q); clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q);
break; break;
case _PLL2_R: case _PLL2_R:
clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_R); clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R);
break; break;
case _PLL3_P: case _PLL3_P:
clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
break; break;
case _PLL3_Q: case _PLL3_Q:
clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_Q); clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q);
break; break;
case _PLL3_R: case _PLL3_R:
clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_R); clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R);
break; break;
case _PLL4_P: case _PLL4_P:
clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_P); clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P);
break; break;
case _PLL4_Q: case _PLL4_Q:
clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_Q); clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q);
break; break;
case _PLL4_R: case _PLL4_R:
clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_R); clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R);
break; break;
/* Other */ /* Other */
case _USB_PHY_48: case _USB_PHY_48:
clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); clock = USB_PHY_48_MHZ;
break; break;
default: default:
break; break;
...@@ -777,113 +860,164 @@ static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) ...@@ -777,113 +860,164 @@ static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
return clock; return clock;
} }
bool stm32mp1_clk_is_enabled(unsigned long id) static void __clk_enable(struct stm32mp1_clk_gate const *gate)
{
uintptr_t rcc_base = stm32mp_rcc_base();
if (gate->set_clr != 0U) {
mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));
} else {
mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));
}
VERBOSE("Clock %d has been enabled", gate->index);
}
static void __clk_disable(struct stm32mp1_clk_gate const *gate)
{
uintptr_t rcc_base = stm32mp_rcc_base();
if (gate->set_clr != 0U) {
mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,
BIT(gate->bit));
} else {
mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));
}
VERBOSE("Clock %d has been disabled", gate->index);
}
static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate)
{
uintptr_t rcc_base = stm32mp_rcc_base();
return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);
}
unsigned int stm32mp1_clk_get_refcount(unsigned long id)
{ {
struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; int i = stm32mp1_clk_get_gated_id(id);
const struct stm32mp1_clk_gate *gate = priv->data->gate;
int i = stm32mp1_clk_get_id(priv, id);
if (i < 0) { if (i < 0) {
return false; panic();
} }
return ((mmio_read_32(priv->base + gate[i].offset) & return gate_refcounts[i];
BIT(gate[i].bit)) != 0U);
} }
int stm32mp1_clk_enable(unsigned long id) void __stm32mp1_clk_enable(unsigned long id, bool secure)
{ {
struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; const struct stm32mp1_clk_gate *gate;
const struct stm32mp1_clk_gate *gate = priv->data->gate; int i = stm32mp1_clk_get_gated_id(id);
int i = stm32mp1_clk_get_id(priv, id); unsigned int *refcnt;
if (i < 0) { if (i < 0) {
return i; ERROR("Clock %d can't be enabled\n", (uint32_t)id);
panic();
} }
if (gate[i].set_clr != 0U) { gate = gate_ref(i);
mmio_write_32(priv->base + gate[i].offset, BIT(gate[i].bit)); refcnt = &gate_refcounts[i];
} else {
mmio_setbits_32(priv->base + gate[i].offset, BIT(gate[i].bit)); stm32mp1_clk_lock(&refcount_lock);
if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) {
__clk_enable(gate);
} }
return 0; stm32mp1_clk_unlock(&refcount_lock);
} }
int stm32mp1_clk_disable(unsigned long id) void __stm32mp1_clk_disable(unsigned long id, bool secure)
{ {
struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; const struct stm32mp1_clk_gate *gate;
const struct stm32mp1_clk_gate *gate = priv->data->gate; int i = stm32mp1_clk_get_gated_id(id);
int i = stm32mp1_clk_get_id(priv, id); unsigned int *refcnt;
if (i < 0) { if (i < 0) {
return i; ERROR("Clock %d can't be disabled\n", (uint32_t)id);
panic();
} }
if (gate[i].set_clr != 0U) { gate = gate_ref(i);
mmio_write_32(priv->base + gate[i].offset refcnt = &gate_refcounts[i];
+ RCC_MP_ENCLRR_OFFSET,
BIT(gate[i].bit)); stm32mp1_clk_lock(&refcount_lock);
} else {
mmio_clrbits_32(priv->base + gate[i].offset, BIT(gate[i].bit)); if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) {
__clk_disable(gate);
} }
return 0; stm32mp1_clk_unlock(&refcount_lock);
} }
unsigned long stm32mp1_clk_get_rate(unsigned long id) void stm32mp_clk_enable(unsigned long id)
{ {
struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; __stm32mp1_clk_enable(id, true);
int p = stm32mp1_clk_get_parent(priv, id); }
unsigned long rate;
void stm32mp_clk_disable(unsigned long id)
{
__stm32mp1_clk_disable(id, true);
}
bool stm32mp_clk_is_enabled(unsigned long id)
{
int i = stm32mp1_clk_get_gated_id(id);
if (i < 0) {
panic();
}
return __clk_is_enabled(gate_ref(i));
}
unsigned long stm32mp_clk_get_rate(unsigned long id)
{
int p = stm32mp1_clk_get_parent(id);
if (p < 0) { if (p < 0) {
return 0; return 0;
} }
rate = stm32mp1_clk_get(priv, p); return get_clock_rate(p);
return rate;
} }
static void stm32mp1_ls_osc_set(int enable, uint32_t rcc, uint32_t offset, static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on)
uint32_t mask_on)
{ {
uint32_t address = rcc + offset; uintptr_t address = stm32mp_rcc_base() + offset;
if (enable != 0) { if (enable) {
mmio_setbits_32(address, mask_on); mmio_setbits_32(address, mask_on);
} else { } else {
mmio_clrbits_32(address, mask_on); mmio_clrbits_32(address, mask_on);
} }
} }
static void stm32mp1_hs_ocs_set(int enable, uint32_t rcc, uint32_t mask_on) static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on)
{ {
if (enable != 0) { uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR;
mmio_setbits_32(rcc + RCC_OCENSETR, mask_on); uintptr_t address = stm32mp_rcc_base() + offset;
} else {
mmio_setbits_32(rcc + RCC_OCENCLRR, mask_on); mmio_write_32(address, mask_on);
}
} }
static int stm32mp1_osc_wait(int enable, uint32_t rcc, uint32_t offset, static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy)
uint32_t mask_rdy)
{ {
unsigned long start; uint64_t timeout;
uint32_t mask_test; uint32_t mask_test;
uint32_t address = rcc + offset; uintptr_t address = stm32mp_rcc_base() + offset;
if (enable != 0) { if (enable) {
mask_test = mask_rdy; mask_test = mask_rdy;
} else { } else {
mask_test = 0; mask_test = 0;
} }
start = get_timer(0); timeout = timeout_init_us(OSCRDY_TIMEOUT);
while ((mmio_read_32(address) & mask_rdy) != mask_test) { while ((mmio_read_32(address) & mask_rdy) != mask_test) {
if (get_timer(start) > OSCRDY_TIMEOUT) { if (timeout_elapsed(timeout)) {
ERROR("OSC %x @ %x timeout for enable=%d : 0x%x\n", ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n",
mask_rdy, address, enable, mmio_read_32(address)); mask_rdy, address, enable, mmio_read_32(address));
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -892,19 +1026,24 @@ static int stm32mp1_osc_wait(int enable, uint32_t rcc, uint32_t offset, ...@@ -892,19 +1026,24 @@ static int stm32mp1_osc_wait(int enable, uint32_t rcc, uint32_t offset,
return 0; return 0;
} }
static void stm32mp1_lse_enable(uint32_t rcc, bool bypass, uint32_t lsedrv) static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv)
{ {
uint32_t value; uint32_t value;
uintptr_t rcc_base = stm32mp_rcc_base();
if (digbyp) {
mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);
}
if (bypass) { if (bypass || digbyp) {
mmio_setbits_32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);
} }
/* /*
* Warning: not recommended to switch directly from "high drive" * Warning: not recommended to switch directly from "high drive"
* to "medium low drive", and vice-versa. * to "medium low drive", and vice-versa.
*/ */
value = (mmio_read_32(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>
RCC_BDCR_LSEDRV_SHIFT; RCC_BDCR_LSEDRV_SHIFT;
while (value != lsedrv) { while (value != lsedrv) {
...@@ -914,78 +1053,82 @@ static void stm32mp1_lse_enable(uint32_t rcc, bool bypass, uint32_t lsedrv) ...@@ -914,78 +1053,82 @@ static void stm32mp1_lse_enable(uint32_t rcc, bool bypass, uint32_t lsedrv)
value++; value++;
} }
mmio_clrsetbits_32(rcc + RCC_BDCR, mmio_clrsetbits_32(rcc_base + RCC_BDCR,
RCC_BDCR_LSEDRV_MASK, RCC_BDCR_LSEDRV_MASK,
value << RCC_BDCR_LSEDRV_SHIFT); value << RCC_BDCR_LSEDRV_SHIFT);
} }
stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON);
} }
static void stm32mp1_lse_wait(uint32_t rcc) static void stm32mp1_lse_wait(void)
{ {
if (stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) {
VERBOSE("%s: failed\n", __func__); VERBOSE("%s: failed\n", __func__);
} }
} }
static void stm32mp1_lsi_set(uint32_t rcc, int enable) static void stm32mp1_lsi_set(bool enable)
{ {
stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION);
if (stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) !=
0) { if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) {
VERBOSE("%s: failed\n", __func__); VERBOSE("%s: failed\n", __func__);
} }
} }
static void stm32mp1_hse_enable(uint32_t rcc, bool bypass, bool css) static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css)
{ {
if (bypass) { uintptr_t rcc_base = stm32mp_rcc_base();
mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
if (digbyp) {
mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);
}
if (bypass || digbyp) {
mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);
} }
stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON);
if (stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) {
0) {
VERBOSE("%s: failed\n", __func__); VERBOSE("%s: failed\n", __func__);
} }
if (css) { if (css) {
mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON); mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
} }
} }
static void stm32mp1_csi_set(uint32_t rcc, int enable) static void stm32mp1_csi_set(bool enable)
{ {
stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION); stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION);
if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) {
0) {
VERBOSE("%s: failed\n", __func__); VERBOSE("%s: failed\n", __func__);
} }
} }
static void stm32mp1_hsi_set(uint32_t rcc, int enable) static void stm32mp1_hsi_set(bool enable)
{ {
stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION);
if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) {
0) {
VERBOSE("%s: failed\n", __func__); VERBOSE("%s: failed\n", __func__);
} }
} }
static int stm32mp1_set_hsidiv(uint32_t rcc, uint8_t hsidiv) static int stm32mp1_set_hsidiv(uint8_t hsidiv)
{ {
unsigned long start; uint64_t timeout;
uint32_t address = rcc + RCC_OCRDYR; uintptr_t rcc_base = stm32mp_rcc_base();
uintptr_t address = rcc_base + RCC_OCRDYR;
mmio_clrsetbits_32(rcc + RCC_HSICFGR, mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
RCC_HSICFGR_HSIDIV_MASK, RCC_HSICFGR_HSIDIV_MASK,
RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
start = get_timer(0); timeout = timeout_init_us(HSIDIV_TIMEOUT);
while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
if (get_timer(start) > HSIDIV_TIMEOUT) { if (timeout_elapsed(timeout)) {
ERROR("HSIDIV failed @ 0x%x: 0x%x\n", ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
address, mmio_read_32(address)); address, mmio_read_32(address));
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -994,7 +1137,7 @@ static int stm32mp1_set_hsidiv(uint32_t rcc, uint8_t hsidiv) ...@@ -994,7 +1137,7 @@ static int stm32mp1_set_hsidiv(uint32_t rcc, uint8_t hsidiv)
return 0; return 0;
} }
static int stm32mp1_hsidiv(uint32_t rcc, unsigned long hsifreq) static int stm32mp1_hsidiv(unsigned long hsifreq)
{ {
uint8_t hsidiv; uint8_t hsidiv;
uint32_t hsidivfreq = MAX_HSI_HZ; uint32_t hsidivfreq = MAX_HSI_HZ;
...@@ -1013,32 +1156,102 @@ static int stm32mp1_hsidiv(uint32_t rcc, unsigned long hsifreq) ...@@ -1013,32 +1156,102 @@ static int stm32mp1_hsidiv(uint32_t rcc, unsigned long hsifreq)
} }
if (hsidiv != 0U) { if (hsidiv != 0U) {
return stm32mp1_set_hsidiv(rcc, hsidiv); return stm32mp1_set_hsidiv(hsidiv);
} }
return 0; return 0;
} }
static void stm32mp1_pll_start(struct stm32mp1_clk_priv *priv, static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,
enum stm32mp1_pll_id pll_id) unsigned int clksrc,
uint32_t *pllcfg, int plloff)
{ {
const struct stm32mp1_clk_pll *pll = priv->data->pll; const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
uintptr_t rcc_base = stm32mp_rcc_base();
uintptr_t pllxcr = rcc_base + pll->pllxcr;
enum stm32mp1_plltype type = pll->plltype;
uintptr_t clksrc_address = rcc_base + (clksrc >> 4);
unsigned long refclk;
uint32_t ifrge = 0U;
uint32_t src, value, fracv;
/* Check PLL output */
if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) {
return false;
}
/* Check current clksrc */
src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK;
if (src != (clksrc & RCC_SELR_SRC_MASK)) {
return false;
}
/* Check Div */
src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;
refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
(pllcfg[PLLCFG_M] + 1U);
if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
(refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
return false;
}
if ((type == PLL_800) && (refclk >= 8000000U)) {
ifrge = 1U;
}
value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
RCC_PLLNCFGR1_DIVN_MASK;
value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
RCC_PLLNCFGR1_DIVM_MASK;
value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
RCC_PLLNCFGR1_IFRGE_MASK;
if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {
return false;
}
/* Fractional configuration */
fracv = fdt_read_uint32_default(plloff, "frac", 0);
mmio_write_32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_PLLON); value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
value |= RCC_PLLNFRACR_FRACLE;
if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {
return false;
}
/* Output config */
value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
RCC_PLLNCFGR2_DIVP_MASK;
value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
RCC_PLLNCFGR2_DIVQ_MASK;
value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
RCC_PLLNCFGR2_DIVR_MASK;
if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {
return false;
}
return true;
}
static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)
{
const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
mmio_write_32(pllxcr, RCC_PLLNCR_PLLON);
} }
static int stm32mp1_pll_output(struct stm32mp1_clk_priv *priv, static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output)
enum stm32mp1_pll_id pll_id, uint32_t output)
{ {
const struct stm32mp1_clk_pll *pll = priv->data->pll; const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
unsigned long start; uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
start = get_timer(0);
/* Wait PLL lock */ /* Wait PLL lock */
while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
if (get_timer(start) > PLLRDY_TIMEOUT) { if (timeout_elapsed(timeout)) {
ERROR("PLL%d start failed @ 0x%x: 0x%x\n", ERROR("PLL%d start failed @ 0x%lx: 0x%x\n",
pll_id, pllxcr, mmio_read_32(pllxcr)); pll_id, pllxcr, mmio_read_32(pllxcr));
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -1050,12 +1263,11 @@ static int stm32mp1_pll_output(struct stm32mp1_clk_priv *priv, ...@@ -1050,12 +1263,11 @@ static int stm32mp1_pll_output(struct stm32mp1_clk_priv *priv,
return 0; return 0;
} }
static int stm32mp1_pll_stop(struct stm32mp1_clk_priv *priv, static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)
enum stm32mp1_pll_id pll_id)
{ {
const struct stm32mp1_clk_pll *pll = priv->data->pll; const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
unsigned long start; uint64_t timeout;
/* Stop all output */ /* Stop all output */
mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
...@@ -1064,11 +1276,11 @@ static int stm32mp1_pll_stop(struct stm32mp1_clk_priv *priv, ...@@ -1064,11 +1276,11 @@ static int stm32mp1_pll_stop(struct stm32mp1_clk_priv *priv,
/* Stop PLL */ /* Stop PLL */
mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON);
start = get_timer(0); timeout = timeout_init_us(PLLRDY_TIMEOUT);
/* Wait PLL stopped */ /* Wait PLL stopped */
while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
if (get_timer(start) > PLLRDY_TIMEOUT) { if (timeout_elapsed(timeout)) {
ERROR("PLL%d stop failed @ 0x%x: 0x%x\n", ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n",
pll_id, pllxcr, mmio_read_32(pllxcr)); pll_id, pllxcr, mmio_read_32(pllxcr));
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -1077,12 +1289,11 @@ static int stm32mp1_pll_stop(struct stm32mp1_clk_priv *priv, ...@@ -1077,12 +1289,11 @@ static int stm32mp1_pll_stop(struct stm32mp1_clk_priv *priv,
return 0; return 0;
} }
static void stm32mp1_pll_config_output(struct stm32mp1_clk_priv *priv, static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,
enum stm32mp1_pll_id pll_id,
uint32_t *pllcfg) uint32_t *pllcfg)
{ {
const struct stm32mp1_clk_pll *pll = priv->data->pll; const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
uint32_t rcc = priv->base; uintptr_t rcc_base = stm32mp_rcc_base();
uint32_t value; uint32_t value;
value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
...@@ -1091,24 +1302,23 @@ static void stm32mp1_pll_config_output(struct stm32mp1_clk_priv *priv, ...@@ -1091,24 +1302,23 @@ static void stm32mp1_pll_config_output(struct stm32mp1_clk_priv *priv,
RCC_PLLNCFGR2_DIVQ_MASK; RCC_PLLNCFGR2_DIVQ_MASK;
value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
RCC_PLLNCFGR2_DIVR_MASK; RCC_PLLNCFGR2_DIVR_MASK;
mmio_write_32(rcc + pll[pll_id].pllxcfgr2, value); mmio_write_32(rcc_base + pll->pllxcfgr2, value);
} }
static int stm32mp1_pll_config(struct stm32mp1_clk_priv *priv, static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,
enum stm32mp1_pll_id pll_id,
uint32_t *pllcfg, uint32_t fracv) uint32_t *pllcfg, uint32_t fracv)
{ {
const struct stm32mp1_clk_pll *pll = priv->data->pll; const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
uint32_t rcc = priv->base; uintptr_t rcc_base = stm32mp_rcc_base();
enum stm32mp1_plltype type = pll[pll_id].plltype; enum stm32mp1_plltype type = pll->plltype;
unsigned long refclk; unsigned long refclk;
uint32_t ifrge = 0; uint32_t ifrge = 0;
uint32_t src, value; uint32_t src, value;
src = mmio_read_32(priv->base + pll[pll_id].rckxselr) & src = mmio_read_32(rcc_base + pll->rckxselr) &
RCC_SELR_REFCLK_SRC_MASK; RCC_SELR_REFCLK_SRC_MASK;
refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) / refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
(pllcfg[PLLCFG_M] + 1U); (pllcfg[PLLCFG_M] + 1U);
if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
...@@ -1126,28 +1336,26 @@ static int stm32mp1_pll_config(struct stm32mp1_clk_priv *priv, ...@@ -1126,28 +1336,26 @@ static int stm32mp1_pll_config(struct stm32mp1_clk_priv *priv,
RCC_PLLNCFGR1_DIVM_MASK; RCC_PLLNCFGR1_DIVM_MASK;
value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
RCC_PLLNCFGR1_IFRGE_MASK; RCC_PLLNCFGR1_IFRGE_MASK;
mmio_write_32(rcc + pll[pll_id].pllxcfgr1, value); mmio_write_32(rcc_base + pll->pllxcfgr1, value);
/* Fractional configuration */ /* Fractional configuration */
value = 0; value = 0;
mmio_write_32(rcc + pll[pll_id].pllxfracr, value); mmio_write_32(rcc_base + pll->pllxfracr, value);
value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
mmio_write_32(rcc + pll[pll_id].pllxfracr, value); mmio_write_32(rcc_base + pll->pllxfracr, value);
value |= RCC_PLLNFRACR_FRACLE; value |= RCC_PLLNFRACR_FRACLE;
mmio_write_32(rcc + pll[pll_id].pllxfracr, value); mmio_write_32(rcc_base + pll->pllxfracr, value);
stm32mp1_pll_config_output(priv, pll_id, pllcfg); stm32mp1_pll_config_output(pll_id, pllcfg);
return 0; return 0;
} }
static void stm32mp1_pll_csg(struct stm32mp1_clk_priv *priv, static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg)
enum stm32mp1_pll_id pll_id,
uint32_t *csg)
{ {
const struct stm32mp1_clk_pll *pll = priv->data->pll; const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
uint32_t pllxcsg = 0; uint32_t pllxcsg = 0;
pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
...@@ -1159,23 +1367,22 @@ static void stm32mp1_pll_csg(struct stm32mp1_clk_priv *priv, ...@@ -1159,23 +1367,22 @@ static void stm32mp1_pll_csg(struct stm32mp1_clk_priv *priv,
pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
RCC_PLLNCSGR_SSCG_MODE_MASK; RCC_PLLNCSGR_SSCG_MODE_MASK;
mmio_write_32(priv->base + pll[pll_id].pllxcsgr, pllxcsg); mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg);
} }
static int stm32mp1_set_clksrc(struct stm32mp1_clk_priv *priv, static int stm32mp1_set_clksrc(unsigned int clksrc)
unsigned int clksrc)
{ {
uint32_t address = priv->base + (clksrc >> 4); uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
unsigned long start; uint64_t timeout;
mmio_clrsetbits_32(address, RCC_SELR_SRC_MASK, mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK,
clksrc & RCC_SELR_SRC_MASK); clksrc & RCC_SELR_SRC_MASK);
start = get_timer(0); timeout = timeout_init_us(CLKSRC_TIMEOUT);
while ((mmio_read_32(address) & RCC_SELR_SRCRDY) == 0U) { while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) {
if (get_timer(start) > CLKSRC_TIMEOUT) { if (timeout_elapsed(timeout)) {
ERROR("CLKSRC %x start failed @ 0x%x: 0x%x\n", ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc,
clksrc, address, mmio_read_32(address)); clksrc_address, mmio_read_32(clksrc_address));
return -ETIMEDOUT; return -ETIMEDOUT;
} }
} }
...@@ -1183,17 +1390,17 @@ static int stm32mp1_set_clksrc(struct stm32mp1_clk_priv *priv, ...@@ -1183,17 +1390,17 @@ static int stm32mp1_set_clksrc(struct stm32mp1_clk_priv *priv,
return 0; return 0;
} }
static int stm32mp1_set_clkdiv(unsigned int clkdiv, uint32_t address) static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address)
{ {
unsigned long start; uint64_t timeout;
mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK,
clkdiv & RCC_DIVR_DIV_MASK); clkdiv & RCC_DIVR_DIV_MASK);
start = get_timer(0); timeout = timeout_init_us(CLKDIV_TIMEOUT);
while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) {
if (get_timer(start) > CLKDIV_TIMEOUT) { if (timeout_elapsed(timeout)) {
ERROR("CLKDIV %x start failed @ 0x%x: 0x%x\n", ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n",
clkdiv, address, mmio_read_32(address)); clkdiv, address, mmio_read_32(address));
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -1202,10 +1409,9 @@ static int stm32mp1_set_clkdiv(unsigned int clkdiv, uint32_t address) ...@@ -1202,10 +1409,9 @@ static int stm32mp1_set_clkdiv(unsigned int clkdiv, uint32_t address)
return 0; return 0;
} }
static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv)
uint32_t clksrc, uint32_t clkdiv)
{ {
uint32_t address = priv->base + (clksrc >> 4); uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
/* /*
* Binding clksrc : * Binding clksrc :
...@@ -1214,22 +1420,21 @@ static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, ...@@ -1214,22 +1420,21 @@ static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
* bit2-0: MCOSEL[2:0] * bit2-0: MCOSEL[2:0]
*/ */
if ((clksrc & 0x8U) != 0U) { if ((clksrc & 0x8U) != 0U) {
mmio_clrbits_32(address, RCC_MCOCFG_MCOON); mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON);
} else { } else {
mmio_clrsetbits_32(address, mmio_clrsetbits_32(clksrc_address,
RCC_MCOCFG_MCOSRC_MASK, RCC_MCOCFG_MCOSRC_MASK,
clksrc & RCC_MCOCFG_MCOSRC_MASK); clksrc & RCC_MCOCFG_MCOSRC_MASK);
mmio_clrsetbits_32(address, mmio_clrsetbits_32(clksrc_address,
RCC_MCOCFG_MCODIV_MASK, RCC_MCOCFG_MCODIV_MASK,
clkdiv << RCC_MCOCFG_MCODIV_SHIFT); clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
mmio_setbits_32(address, RCC_MCOCFG_MCOON); mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON);
} }
} }
static void stm32mp1_set_rtcsrc(struct stm32mp1_clk_priv *priv, static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
unsigned int clksrc, bool lse_css)
{ {
uint32_t address = priv->base + RCC_BDCR; uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) ||
(clksrc != (uint32_t)CLK_RTC_DISABLED)) { (clksrc != (uint32_t)CLK_RTC_DISABLED)) {
...@@ -1248,38 +1453,35 @@ static void stm32mp1_set_rtcsrc(struct stm32mp1_clk_priv *priv, ...@@ -1248,38 +1453,35 @@ static void stm32mp1_set_rtcsrc(struct stm32mp1_clk_priv *priv,
#define CNTCVL_OFF 0x008 #define CNTCVL_OFF 0x008
#define CNTCVU_OFF 0x00C #define CNTCVU_OFF 0x00C
static void stm32mp1_stgen_config(struct stm32mp1_clk_priv *priv) static void stm32mp1_stgen_config(void)
{ {
uintptr_t stgen; uintptr_t stgen;
int p;
uint32_t cntfid0; uint32_t cntfid0;
unsigned long rate; unsigned long rate;
unsigned long long counter;
stgen = fdt_get_stgen_base(); stgen = fdt_get_stgen_base();
cntfid0 = mmio_read_32(stgen + CNTFID_OFF); cntfid0 = mmio_read_32(stgen + CNTFID_OFF);
p = stm32mp1_clk_get_parent(priv, STGEN_K); rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K));
rate = stm32mp1_clk_get(priv, p);
if (cntfid0 != rate) { if (cntfid0 == rate) {
unsigned long long counter; return;
}
mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
counter = (unsigned long long) counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF);
mmio_read_32(stgen + CNTCVL_OFF); counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32;
counter |= ((unsigned long long) counter = (counter * rate / cntfid0);
(mmio_read_32(stgen + CNTCVU_OFF))) << 32;
counter = (counter * rate / cntfid0);
mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter);
mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32));
mmio_write_32(stgen + CNTFID_OFF, rate);
mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
write_cntfrq((u_register_t)rate); mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter);
mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32));
mmio_write_32(stgen + CNTFID_OFF, rate);
mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
/* Need to update timer with new frequency */ write_cntfrq((u_register_t)rate);
generic_delay_timer_init();
} /* Need to update timer with new frequency */
generic_delay_timer_init();
} }
void stm32mp1_stgen_increment(unsigned long long offset_in_ms) void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
...@@ -1300,9 +1502,9 @@ void stm32mp1_stgen_increment(unsigned long long offset_in_ms) ...@@ -1300,9 +1502,9 @@ void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
} }
static void stm32mp1_pkcs_config(struct stm32mp1_clk_priv *priv, uint32_t pkcs) static void stm32mp1_pkcs_config(uint32_t pkcs)
{ {
uint32_t address = priv->base + ((pkcs >> 4) & 0xFFFU); uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU);
uint32_t value = pkcs & 0xFU; uint32_t value = pkcs & 0xFU;
uint32_t mask = 0xFU; uint32_t mask = 0xFU;
...@@ -1316,8 +1518,7 @@ static void stm32mp1_pkcs_config(struct stm32mp1_clk_priv *priv, uint32_t pkcs) ...@@ -1316,8 +1518,7 @@ static void stm32mp1_pkcs_config(struct stm32mp1_clk_priv *priv, uint32_t pkcs)
int stm32mp1_clk_init(void) int stm32mp1_clk_init(void)
{ {
struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; uintptr_t rcc_base = stm32mp_rcc_base();
uint32_t rcc = priv->base;
unsigned int clksrc[CLKSRC_NB]; unsigned int clksrc[CLKSRC_NB];
unsigned int clkdiv[CLKDIV_NB]; unsigned int clkdiv[CLKDIV_NB];
unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
...@@ -1325,11 +1526,14 @@ int stm32mp1_clk_init(void) ...@@ -1325,11 +1526,14 @@ int stm32mp1_clk_init(void)
int ret, len; int ret, len;
enum stm32mp1_pll_id i; enum stm32mp1_pll_id i;
bool lse_css = false; bool lse_css = false;
bool pll3_preserve = false;
bool pll4_preserve = false;
bool pll4_bootrom = false;
const fdt32_t *pkcs_cell; const fdt32_t *pkcs_cell;
/* Check status field to disable security */ /* Check status field to disable security */
if (!fdt_get_rcc_secure_status()) { if (!fdt_get_rcc_secure_status()) {
mmio_write_32(rcc + RCC_TZCR, 0); mmio_write_32(rcc_base + RCC_TZCR, 0);
} }
ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc, ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc,
...@@ -1361,113 +1565,135 @@ int stm32mp1_clk_init(void) ...@@ -1361,113 +1565,135 @@ int stm32mp1_clk_init(void)
} }
} }
stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
/* /*
* Switch ON oscillator found in device-tree. * Switch ON oscillator found in device-tree.
* Note: HSI already ON after BootROM stage. * Note: HSI already ON after BootROM stage.
*/ */
if (priv->osc[_LSI] != 0U) { if (stm32mp1_osc[_LSI] != 0U) {
stm32mp1_lsi_set(rcc, 1); stm32mp1_lsi_set(true);
} }
if (priv->osc[_LSE] != 0U) { if (stm32mp1_osc[_LSE] != 0U) {
bool bypass; bool bypass, digbyp;
uint32_t lsedrv; uint32_t lsedrv;
bypass = fdt_osc_read_bool(_LSE, "st,bypass"); bypass = fdt_osc_read_bool(_LSE, "st,bypass");
digbyp = fdt_osc_read_bool(_LSE, "st,digbypass");
lse_css = fdt_osc_read_bool(_LSE, "st,css"); lse_css = fdt_osc_read_bool(_LSE, "st,css");
lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive",
LSEDRV_MEDIUM_HIGH); LSEDRV_MEDIUM_HIGH);
stm32mp1_lse_enable(rcc, bypass, lsedrv); stm32mp1_lse_enable(bypass, digbyp, lsedrv);
} }
if (priv->osc[_HSE] != 0U) { if (stm32mp1_osc[_HSE] != 0U) {
bool bypass, css; bool bypass, digbyp, css;
bypass = fdt_osc_read_bool(_LSE, "st,bypass"); bypass = fdt_osc_read_bool(_HSE, "st,bypass");
css = fdt_osc_read_bool(_LSE, "st,css"); digbyp = fdt_osc_read_bool(_HSE, "st,digbypass");
stm32mp1_hse_enable(rcc, bypass, css); css = fdt_osc_read_bool(_HSE, "st,css");
stm32mp1_hse_enable(bypass, digbyp, css);
} }
/* /*
* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
* => switch on CSI even if node is not present in device tree * => switch on CSI even if node is not present in device tree
*/ */
stm32mp1_csi_set(rcc, 1); stm32mp1_csi_set(true);
/* Come back to HSI */ /* Come back to HSI */
ret = stm32mp1_set_clksrc(priv, CLK_MPU_HSI); ret = stm32mp1_set_clksrc(CLK_MPU_HSI);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
ret = stm32mp1_set_clksrc(priv, CLK_AXI_HSI); ret = stm32mp1_set_clksrc(CLK_AXI_HSI);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &
RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) {
pll3_preserve = stm32mp1_check_pll_conf(_PLL3,
clksrc[CLKSRC_PLL3],
pllcfg[_PLL3],
plloff[_PLL3]);
pll4_preserve = stm32mp1_check_pll_conf(_PLL4,
clksrc[CLKSRC_PLL4],
pllcfg[_PLL4],
plloff[_PLL4]);
}
for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
if (i == _PLL4) if (((i == _PLL3) && pll3_preserve) ||
((i == _PLL4) && pll4_preserve)) {
continue; continue;
ret = stm32mp1_pll_stop(priv, i); }
ret = stm32mp1_pll_stop(i);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
} }
/* Configure HSIDIV */ /* Configure HSIDIV */
if (priv->osc[_HSI] != 0U) { if (stm32mp1_osc[_HSI] != 0U) {
ret = stm32mp1_hsidiv(rcc, priv->osc[_HSI]); ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
stm32mp1_stgen_config(priv); stm32mp1_stgen_config();
} }
/* Select DIV */ /* Select DIV */
/* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
mmio_write_32(rcc + RCC_MPCKDIVR, mmio_write_32(rcc_base + RCC_MPCKDIVR,
clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK);
ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
/* No ready bit for RTC */ /* No ready bit for RTC */
mmio_write_32(rcc + RCC_RTCDIVR, mmio_write_32(rcc_base + RCC_RTCDIVR,
clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK);
/* Configure PLLs source */ /* Configure PLLs source */
ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL12]); ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL3]);
if (ret != 0) { if (!pll3_preserve) {
return ret; ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]);
if (ret != 0) {
return ret;
}
} }
ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL4]); if (!pll4_preserve) {
if (ret != 0) { ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]);
return ret; if (ret != 0) {
return ret;
}
} }
/* Configure and start PLLs */ /* Configure and start PLLs */
...@@ -1475,25 +1701,36 @@ int stm32mp1_clk_init(void) ...@@ -1475,25 +1701,36 @@ int stm32mp1_clk_init(void)
uint32_t fracv; uint32_t fracv;
uint32_t csg[PLLCSG_NB]; uint32_t csg[PLLCSG_NB];
if (((i == _PLL3) && pll3_preserve) ||
((i == _PLL4) && pll4_preserve && !pll4_bootrom)) {
continue;
}
if (!fdt_check_node(plloff[i])) { if (!fdt_check_node(plloff[i])) {
continue; continue;
} }
if ((i == _PLL4) && pll4_bootrom) {
/* Set output divider if not done by the Bootrom */
stm32mp1_pll_config_output(i, pllcfg[i]);
continue;
}
fracv = fdt_read_uint32_default(plloff[i], "frac", 0); fracv = fdt_read_uint32_default(plloff[i], "frac", 0);
ret = stm32mp1_pll_config(priv, i, pllcfg[i], fracv); ret = stm32mp1_pll_config(i, pllcfg[i], fracv);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
ret = fdt_read_uint32_array(plloff[i], "csg", csg, ret = fdt_read_uint32_array(plloff[i], "csg", csg,
(uint32_t)PLLCSG_NB); (uint32_t)PLLCSG_NB);
if (ret == 0) { if (ret == 0) {
stm32mp1_pll_csg(priv, i, csg); stm32mp1_pll_csg(i, csg);
} else if (ret != -FDT_ERR_NOTFOUND) { } else if (ret != -FDT_ERR_NOTFOUND) {
return ret; return ret;
} }
stm32mp1_pll_start(priv, i); stm32mp1_pll_start(i);
} }
/* Wait and start PLLs ouptut when ready */ /* Wait and start PLLs ouptut when ready */
for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
...@@ -1501,26 +1738,26 @@ int stm32mp1_clk_init(void) ...@@ -1501,26 +1738,26 @@ int stm32mp1_clk_init(void)
continue; continue;
} }
ret = stm32mp1_pll_output(priv, i, pllcfg[i][PLLCFG_O]); ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
} }
/* Wait LSE ready before to use it */ /* Wait LSE ready before to use it */
if (priv->osc[_LSE] != 0U) { if (stm32mp1_osc[_LSE] != 0U) {
stm32mp1_lse_wait(rcc); stm32mp1_lse_wait();
} }
/* Configure with expected clock source */ /* Configure with expected clock source */
ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_MPU]); ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_AXI]); ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
stm32mp1_set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css);
/* Configure PKCK */ /* Configure PKCK */
pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len);
...@@ -1528,8 +1765,6 @@ int stm32mp1_clk_init(void) ...@@ -1528,8 +1765,6 @@ int stm32mp1_clk_init(void)
bool ckper_disabled = false; bool ckper_disabled = false;
uint32_t j; uint32_t j;
priv->pkcs_usb_value = 0;
for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) {
uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]);
...@@ -1537,7 +1772,7 @@ int stm32mp1_clk_init(void) ...@@ -1537,7 +1772,7 @@ int stm32mp1_clk_init(void)
ckper_disabled = true; ckper_disabled = true;
continue; continue;
} }
stm32mp1_pkcs_config(priv, pkcs); stm32mp1_pkcs_config(pkcs);
} }
/* /*
...@@ -1547,18 +1782,18 @@ int stm32mp1_clk_init(void) ...@@ -1547,18 +1782,18 @@ int stm32mp1_clk_init(void)
* => deactivated CKPER only after switching clock * => deactivated CKPER only after switching clock
*/ */
if (ckper_disabled) { if (ckper_disabled) {
stm32mp1_pkcs_config(priv, CLK_CKPER_DISABLED); stm32mp1_pkcs_config(CLK_CKPER_DISABLED);
} }
} }
/* Switch OFF HSI if not found in device-tree */ /* Switch OFF HSI if not found in device-tree */
if (priv->osc[_HSI] == 0U) { if (stm32mp1_osc[_HSI] == 0U) {
stm32mp1_hsi_set(rcc, 0); stm32mp1_hsi_set(false);
} }
stm32mp1_stgen_config(priv); stm32mp1_stgen_config();
/* Software Self-Refresh mode (SSR) during DDR initilialization */ /* Software Self-Refresh mode (SSR) during DDR initilialization */
mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,
RCC_DDRITFCR_DDRCKMOD_MASK, RCC_DDRITFCR_DDRCKMOD_MASK,
RCC_DDRITFCR_DDRCKMOD_SSR << RCC_DDRITFCR_DDRCKMOD_SSR <<
RCC_DDRITFCR_DDRCKMOD_SHIFT); RCC_DDRITFCR_DDRCKMOD_SHIFT);
...@@ -1567,47 +1802,26 @@ int stm32mp1_clk_init(void) ...@@ -1567,47 +1802,26 @@ int stm32mp1_clk_init(void)
} }
static void stm32mp1_osc_clk_init(const char *name, static void stm32mp1_osc_clk_init(const char *name,
struct stm32mp1_clk_priv *priv,
enum stm32mp_osc_id index) enum stm32mp_osc_id index)
{ {
uint32_t frequency; uint32_t frequency;
priv->osc[index] = 0; if (fdt_osc_read_freq(name, &frequency) == 0) {
stm32mp1_osc[index] = frequency;
if (fdt_osc_read_freq(name, &frequency) != 0) {
ERROR("%s frequency request failed\n", name);
panic();
} else {
priv->osc[index] = frequency;
} }
} }
static void stm32mp1_osc_init(void) static void stm32mp1_osc_init(void)
{ {
struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
enum stm32mp_osc_id i; enum stm32mp_osc_id i;
for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) {
stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], priv, i); stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i);
} }
} }
int stm32mp1_clk_probe(void) int stm32mp1_clk_probe(void)
{ {
struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
priv->base = fdt_rcc_read_addr();
if (priv->base == 0U) {
return -EINVAL;
}
priv->data = &stm32mp1_data;
if ((priv->data->gate == NULL) || (priv->data->sel == NULL) ||
(priv->data->pll == NULL)) {
return -EINVAL;
}
stm32mp1_osc_init(); stm32mp1_osc_init();
return 0; return 0;
......
drivers/st/clk/stm32mp1_clkfunc.c
View file @ 37cdad2a
...@@ -10,17 +10,12 @@ ...@@ -10,17 +10,12 @@
#include <platform_def.h> #include <platform_def.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <drivers/st/stm32mp1_clk.h> #include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_clkfunc.h> #include <drivers/st/stm32mp1_clkfunc.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h> #include <dt-bindings/clock/stm32mp1-clksrc.h>
#define DT_RCC_NODE_NAME "rcc@50000000"
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
#define DT_RCC_COMPAT "syscon"
#define DT_STGEN_COMPAT "st,stm32-stgen"
#define DT_UART_COMPAT "st,stm32h7-uart"
#define DT_USART_COMPAT "st,stm32h7-usart"
const char *stm32mp_osc_node_label[NB_OSC] = { const char *stm32mp_osc_node_label[NB_OSC] = {
[_LSI] = "clk-lsi", [_LSI] = "clk-lsi",
[_LSE] = "clk-lse", [_LSE] = "clk-lse",
...@@ -28,23 +23,14 @@ const char *stm32mp_osc_node_label[NB_OSC] = { ...@@ -28,23 +23,14 @@ const char *stm32mp_osc_node_label[NB_OSC] = {
[_HSE] = "clk-hse", [_HSE] = "clk-hse",
[_CSI] = "clk-csi", [_CSI] = "clk-csi",
[_I2S_CKIN] = "i2s_ckin", [_I2S_CKIN] = "i2s_ckin",
[_USB_PHY_48] = "ck_usbo_48m"
}; };
/******************************************************************************* /*
* This function returns the RCC node in the device tree. * Get the frequency of an oscillator from its name in device tree.
******************************************************************************/ * @param name: oscillator name
static int fdt_get_rcc_node(void *fdt) * @param freq: stores the frequency of the oscillator
{ * @return: 0 on success, and a negative FDT/ERRNO error code on failure.
return fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); */
}
/*******************************************************************************
* This function reads the frequency of an oscillator from its name.
* It reads the value indicated inside the device tree.
* Returns 0 on success, and a negative FDT/ERRNO error code on failure.
* On success, value is stored in the second parameter.
******************************************************************************/
int fdt_osc_read_freq(const char *name, uint32_t *freq) int fdt_osc_read_freq(const char *name, uint32_t *freq)
{ {
int node, subnode; int node, subnode;
...@@ -88,11 +74,12 @@ int fdt_osc_read_freq(const char *name, uint32_t *freq) ...@@ -88,11 +74,12 @@ int fdt_osc_read_freq(const char *name, uint32_t *freq)
return 0; return 0;
} }
/******************************************************************************* /*
* This function checks the presence of an oscillator property from its id. * Check the presence of an oscillator property from its id.
* The search is done inside the device tree. * @param osc_id: oscillator ID
* Returns true/false regarding search result. * @param prop_name: property name
******************************************************************************/ * @return: true/false regarding search result.
*/
bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name) bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
{ {
int node, subnode; int node, subnode;
...@@ -133,11 +120,13 @@ bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name) ...@@ -133,11 +120,13 @@ bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
return false; return false;
} }
/******************************************************************************* /*
* This function reads a value of a oscillator property from its id. * Get the value of a oscillator property from its ID.
* Returns value on success, and a default value if property not found. * @param osc_id: oscillator ID
* Default value is passed as parameter. * @param prop_name: property name
******************************************************************************/ * @param dflt_value: default value
* @return oscillator value on success, default value if property not found.
*/
uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
const char *prop_name, uint32_t dflt_value) const char *prop_name, uint32_t dflt_value)
{ {
...@@ -176,201 +165,3 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, ...@@ -176,201 +165,3 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
return dflt_value; return dflt_value;
} }
/*******************************************************************************
* This function reads the rcc base address.
* It reads the value indicated inside the device tree.
* Returns address if success, and 0 value else.
******************************************************************************/
uint32_t fdt_rcc_read_addr(void)
{
int node, subnode;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_path_offset(fdt, "/soc");
if (node < 0) {
return 0;
}
fdt_for_each_subnode(subnode, fdt, node) {
const char *cchar;
int ret;
cchar = fdt_get_name(fdt, subnode, &ret);
if (cchar == NULL) {
return 0;
}
if (strncmp(cchar, DT_RCC_NODE_NAME, (size_t)ret) == 0) {
const fdt32_t *cuint;
cuint = fdt_getprop(fdt, subnode, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
}
return 0;
}
/*******************************************************************************
* This function reads a series of parameters in rcc-clk section.
* It reads the values indicated inside the device tree, from property name.
* The number of parameters is also indicated as entry parameter.
* Returns 0 if success, and a negative value else.
* If success, values are stored at the second parameter address.
******************************************************************************/
int fdt_rcc_read_uint32_array(const char *prop_name,
uint32_t *array, uint32_t count)
{
int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
if (node < 0) {
return -FDT_ERR_NOTFOUND;
}
return fdt_read_uint32_array(node, prop_name, array, count);
}
/*******************************************************************************
* This function gets the subnode offset in rcc-clk section from its name.
* It reads the values indicated inside the device tree.
* Returns offset on success, and a negative FDT/ERRNO error code on failure.
******************************************************************************/
int fdt_rcc_subnode_offset(const char *name)
{
int node, subnode;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return -FDT_ERR_NOTFOUND;
}
subnode = fdt_subnode_offset(fdt, node, name);
if (subnode <= 0) {
return -FDT_ERR_NOTFOUND;
}
return subnode;
}
/*******************************************************************************
* This function gets the pointer to a rcc-clk property from its name.
* It reads the values indicated inside the device tree.
* Length of the property is stored in the second parameter.
* Returns pointer on success, and NULL value on failure.
******************************************************************************/
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp)
{
const fdt32_t *cuint;
int node, len;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return NULL;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return NULL;
}
cuint = fdt_getprop(fdt, node, prop_name, &len);
if (cuint == NULL) {
return NULL;
}
*lenp = len;
return cuint;
}
/*******************************************************************************
* This function gets the secure status for rcc node.
* It reads secure-status in device tree.
* Returns true if rcc is available from secure world, false if not.
******************************************************************************/
bool fdt_get_rcc_secure_status(void)
{
int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return false;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return false;
}
return (fdt_get_status(node) & DT_SECURE) != 0U;
}
/*******************************************************************************
* This function reads the stgen base address.
* It reads the value indicated inside the device tree.
* Returns address on success, and NULL value on failure.
******************************************************************************/
uintptr_t fdt_get_stgen_base(void)
{
int node;
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*******************************************************************************
* This function gets the clock ID of the given node.
* It reads the value indicated inside the device tree.
* Returns ID on success, and a negative FDT/ERRNO error code on failure.
******************************************************************************/
int fdt_get_clock_id(int node)
{
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
cuint = fdt_getprop(fdt, node, "clocks", NULL);
if (cuint == NULL) {
return -FDT_ERR_NOTFOUND;
}
cuint++;
return (int)fdt32_to_cpu(*cuint);
}
drivers/st/clk/stm32mp_clkfunc.c 0 → 100644
View file @ 37cdad2a
/*
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
#include <libfdt.h>
#include <platform_def.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
#define DT_STGEN_COMPAT "st,stm32-stgen"
/*
* Get the RCC node offset from the device tree
* @param fdt: Device tree reference
* @return: Node offset or a negative value on error
*/
int fdt_get_rcc_node(void *fdt)
{
return fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
}
/*
* Get the RCC base address from the device tree
* @return: RCC address or 0 on error
*/
uint32_t fdt_rcc_read_addr(void)
{
int node;
void *fdt;
const fdt32_t *cuint;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*
* Read a series of parameters in rcc-clk section in device tree
* @param prop_name: Name of the RCC property to be read
* @param array: the array to store the property parameters
* @param count: number of parameters to be read
* @return: 0 on succes or a negative value on error
*/
int fdt_rcc_read_uint32_array(const char *prop_name,
uint32_t *array, uint32_t count)
{
int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return -FDT_ERR_NOTFOUND;
}
return fdt_read_uint32_array(node, prop_name, array, count);
}
/*
* Get the subnode offset in rcc-clk section from its name in device tree
* @param name: name of the RCC property
* @return: offset on success, and a negative FDT/ERRNO error code on failure.
*/
int fdt_rcc_subnode_offset(const char *name)
{
int node, subnode;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return -FDT_ERR_NOTFOUND;
}
subnode = fdt_subnode_offset(fdt, node, name);
if (subnode <= 0) {
return -FDT_ERR_NOTFOUND;
}
return subnode;
}
/*
* Get the pointer to a rcc-clk property from its name.
* @param name: name of the RCC property
* @param lenp: stores the length of the property.
* @return: pointer to the property on success, and NULL value on failure.
*/
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp)
{
const fdt32_t *cuint;
int node, len;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return NULL;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return NULL;
}
cuint = fdt_getprop(fdt, node, prop_name, &len);
if (cuint == NULL) {
return NULL;
}
*lenp = len;
return cuint;
}
/*
* Get the secure status for rcc node in device tree.
* @return: true if rcc is available from secure world, false if not.
*/
bool fdt_get_rcc_secure_status(void)
{
int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return false;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return false;
}
return !!(fdt_get_status(node) & DT_SECURE);
}
/*
* Get the stgen base address.
* @return: address of stgen on success, and NULL value on failure.
*/
uintptr_t fdt_get_stgen_base(void)
{
int node;
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*
* Get the clock ID of the given node in device tree.
* @param node: node offset
* @return: Clock ID on success, and a negative FDT/ERRNO error code on failure.
*/
int fdt_get_clock_id(int node)
{
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
cuint = fdt_getprop(fdt, node, "clocks", NULL);
if (cuint == NULL) {
return -FDT_ERR_NOTFOUND;
}
cuint++;
return (int)fdt32_to_cpu(*cuint);
}
drivers/st/ddr/stm32mp1_ddr.c
View file @ 37cdad2a
...@@ -14,13 +14,10 @@ ...@@ -14,13 +14,10 @@
#include <common/debug.h> #include <common/debug.h>
#include <drivers/delay_timer.h> #include <drivers/delay_timer.h>
#include <drivers/st/stm32mp_pmic.h> #include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_ddr.h> #include <drivers/st/stm32mp1_ddr.h>
#include <drivers/st/stm32mp1_ddr_regs.h> #include <drivers/st/stm32mp1_ddr_regs.h>
#include <drivers/st/stm32mp1_pwr.h> #include <drivers/st/stm32mp1_pwr.h>
#include <drivers/st/stm32mp1_ram.h> #include <drivers/st/stm32mp1_ram.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
...@@ -32,7 +29,7 @@ struct reg_desc { ...@@ -32,7 +29,7 @@ struct reg_desc {
#define INVALID_OFFSET 0xFFU #define INVALID_OFFSET 0xFFU
#define TIMESLOT_1US (plat_get_syscnt_freq2() / 1000000U) #define TIMEOUT_US_1S 1000000U
#define DDRCTL_REG(x, y) \ #define DDRCTL_REG(x, y) \
{ \ { \
...@@ -327,49 +324,43 @@ static void stm32mp1_ddrphy_idone_wait(struct stm32mp1_ddrphy *phy) ...@@ -327,49 +324,43 @@ static void stm32mp1_ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
{ {
uint32_t pgsr; uint32_t pgsr;
int error = 0; int error = 0;
unsigned long start; uint64_t timeout = timeout_init_us(TIMEOUT_US_1S);
unsigned long time0, time;
start = get_timer(0);
time0 = start;
do { do {
pgsr = mmio_read_32((uintptr_t)&phy->pgsr); pgsr = mmio_read_32((uintptr_t)&phy->pgsr);
time = get_timer(start);
if (time != time0) {
VERBOSE(" > [0x%lx] pgsr = 0x%x &\n",
(uintptr_t)&phy->pgsr, pgsr);
VERBOSE(" [0x%lx] pir = 0x%x (time=%lx)\n",
(uintptr_t)&phy->pir,
mmio_read_32((uintptr_t)&phy->pir),
time);
}
time0 = time; VERBOSE(" > [0x%lx] pgsr = 0x%x &\n",
if (time > plat_get_syscnt_freq2()) { (uintptr_t)&phy->pgsr, pgsr);
if (timeout_elapsed(timeout)) {
panic(); panic();
} }
if ((pgsr & DDRPHYC_PGSR_DTERR) != 0U) { if ((pgsr & DDRPHYC_PGSR_DTERR) != 0U) {
VERBOSE("DQS Gate Trainig Error\n"); VERBOSE("DQS Gate Trainig Error\n");
error++; error++;
} }
if ((pgsr & DDRPHYC_PGSR_DTIERR) != 0U) { if ((pgsr & DDRPHYC_PGSR_DTIERR) != 0U) {
VERBOSE("DQS Gate Trainig Intermittent Error\n"); VERBOSE("DQS Gate Trainig Intermittent Error\n");
error++; error++;
} }
if ((pgsr & DDRPHYC_PGSR_DFTERR) != 0U) { if ((pgsr & DDRPHYC_PGSR_DFTERR) != 0U) {
VERBOSE("DQS Drift Error\n"); VERBOSE("DQS Drift Error\n");
error++; error++;
} }
if ((pgsr & DDRPHYC_PGSR_RVERR) != 0U) { if ((pgsr & DDRPHYC_PGSR_RVERR) != 0U) {
VERBOSE("Read Valid Training Error\n"); VERBOSE("Read Valid Training Error\n");
error++; error++;
} }
if ((pgsr & DDRPHYC_PGSR_RVEIRR) != 0U) { if ((pgsr & DDRPHYC_PGSR_RVEIRR) != 0U) {
VERBOSE("Read Valid Training Intermittent Error\n"); VERBOSE("Read Valid Training Intermittent Error\n");
error++; error++;
} }
} while ((pgsr & DDRPHYC_PGSR_IDONE) == 0U && error == 0); } while (((pgsr & DDRPHYC_PGSR_IDONE) == 0U) && (error == 0));
VERBOSE("\n[0x%lx] pgsr = 0x%x\n", VERBOSE("\n[0x%lx] pgsr = 0x%x\n",
(uintptr_t)&phy->pgsr, pgsr); (uintptr_t)&phy->pgsr, pgsr);
} }
...@@ -401,21 +392,19 @@ static void stm32mp1_start_sw_done(struct stm32mp1_ddrctl *ctl) ...@@ -401,21 +392,19 @@ static void stm32mp1_start_sw_done(struct stm32mp1_ddrctl *ctl)
/* Wait quasi dynamic register update */ /* Wait quasi dynamic register update */
static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl) static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
{ {
unsigned long start; uint64_t timeout;
uint32_t swstat; uint32_t swstat;
mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
VERBOSE("[0x%lx] swctl = 0x%x\n", VERBOSE("[0x%lx] swctl = 0x%x\n",
(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
start = get_timer(0); timeout = timeout_init_us(TIMEOUT_US_1S);
do { do {
swstat = mmio_read_32((uintptr_t)&ctl->swstat); swstat = mmio_read_32((uintptr_t)&ctl->swstat);
VERBOSE("[0x%lx] swstat = 0x%x ", VERBOSE("[0x%lx] swstat = 0x%x ",
(uintptr_t)&ctl->swstat, swstat); (uintptr_t)&ctl->swstat, swstat);
VERBOSE("timer in ms 0x%x = start 0x%lx\r", if (timeout_elapsed(timeout)) {
get_timer(0), start);
if (get_timer(start) > plat_get_syscnt_freq2()) {
panic(); panic();
} }
} while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U); } while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U);
...@@ -427,22 +416,21 @@ static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl) ...@@ -427,22 +416,21 @@ static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
/* Wait quasi dynamic register update */ /* Wait quasi dynamic register update */
static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode) static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode)
{ {
unsigned long start; uint64_t timeout;
uint32_t stat; uint32_t stat;
uint32_t operating_mode;
uint32_t selref_type;
int break_loop = 0; int break_loop = 0;
start = get_timer(0); timeout = timeout_init_us(TIMEOUT_US_1S);
for ( ; ; ) { for ( ; ; ) {
uint32_t operating_mode;
uint32_t selref_type;
stat = mmio_read_32((uintptr_t)&priv->ctl->stat); stat = mmio_read_32((uintptr_t)&priv->ctl->stat);
operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK; operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK;
selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK; selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK;
VERBOSE("[0x%lx] stat = 0x%x\n", VERBOSE("[0x%lx] stat = 0x%x\n",
(uintptr_t)&priv->ctl->stat, stat); (uintptr_t)&priv->ctl->stat, stat);
VERBOSE("timer in ms 0x%x = start 0x%lx\r", if (timeout_elapsed(timeout)) {
get_timer(0), start);
if (get_timer(start) > plat_get_syscnt_freq2()) {
panic(); panic();
} }
...@@ -639,7 +627,7 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv) ...@@ -639,7 +627,7 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
*/ */
/* Change Bypass Mode Frequency Range */ /* Change Bypass Mode Frequency Range */
if (stm32mp1_clk_get_rate(DDRPHYC) < 100000000U) { if (stm32mp_clk_get_rate(DDRPHYC) < 100000000U) {
mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr, mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
DDRPHYC_DLLGCR_BPS200); DDRPHYC_DLLGCR_BPS200);
} else { } else {
...@@ -712,7 +700,7 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, ...@@ -712,7 +700,7 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
static int board_ddr_power_init(enum ddr_type ddr_type) static int board_ddr_power_init(enum ddr_type ddr_type)
{ {
if (dt_check_pmic()) { if (dt_pmic_status() > 0) {
return pmic_ddr_power_init(ddr_type); return pmic_ddr_power_init(ddr_type);
} }
......
drivers/st/ddr/stm32mp1_ddr_helpers.c
View file @ 37cdad2a
/* /*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -7,15 +7,18 @@ ...@@ -7,15 +7,18 @@
#include <platform_def.h> #include <platform_def.h>
#include <drivers/st/stm32mp1_ddr_helpers.h> #include <drivers/st/stm32mp1_ddr_helpers.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <lib/mmio.h> #include <lib/mmio.h>
void ddr_enable_clock(void) void ddr_enable_clock(void)
{ {
mmio_setbits_32(RCC_BASE + RCC_DDRITFCR, stm32mp1_clk_rcc_regs_lock();
mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR,
RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC1EN |
RCC_DDRITFCR_DDRC2EN | RCC_DDRITFCR_DDRC2EN |
RCC_DDRITFCR_DDRPHYCEN | RCC_DDRITFCR_DDRPHYCEN |
RCC_DDRITFCR_DDRPHYCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN |
RCC_DDRITFCR_DDRCAPBEN); RCC_DDRITFCR_DDRCAPBEN);
stm32mp1_clk_rcc_regs_unlock();
} }
drivers/st/ddr/stm32mp1_ram.c
View file @ 37cdad2a
...@@ -12,12 +12,9 @@ ...@@ -12,12 +12,9 @@
#include <arch_helpers.h> #include <arch_helpers.h>
#include <common/debug.h> #include <common/debug.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_ddr.h> #include <drivers/st/stm32mp1_ddr.h>
#include <drivers/st/stm32mp1_ddr_helpers.h> #include <drivers/st/stm32mp1_ddr_helpers.h>
#include <drivers/st/stm32mp1_ram.h> #include <drivers/st/stm32mp1_ram.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#define DDR_PATTERN 0xAAAAAAAAU #define DDR_PATTERN 0xAAAAAAAAU
...@@ -31,7 +28,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) ...@@ -31,7 +28,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
ddr_enable_clock(); ddr_enable_clock();
ddrphy_clk = stm32mp1_clk_get_rate(DDRPHYC); ddrphy_clk = stm32mp_clk_get_rate(DDRPHYC);
VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n", VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n",
mem_speed, ddrphy_clk / 1000U); mem_speed, ddrphy_clk / 1000U);
...@@ -65,10 +62,10 @@ static uint32_t ddr_test_data_bus(void) ...@@ -65,10 +62,10 @@ static uint32_t ddr_test_data_bus(void)
uint32_t pattern; uint32_t pattern;
for (pattern = 1U; pattern != 0U; pattern <<= 1) { for (pattern = 1U; pattern != 0U; pattern <<= 1) {
mmio_write_32(STM32MP1_DDR_BASE, pattern); mmio_write_32(STM32MP_DDR_BASE, pattern);
if (mmio_read_32(STM32MP1_DDR_BASE) != pattern) { if (mmio_read_32(STM32MP_DDR_BASE) != pattern) {
return (uint32_t)STM32MP1_DDR_BASE; return (uint32_t)STM32MP_DDR_BASE;
} }
} }
...@@ -92,44 +89,44 @@ static uint32_t ddr_test_addr_bus(void) ...@@ -92,44 +89,44 @@ static uint32_t ddr_test_addr_bus(void)
/* Write the default pattern at each of the power-of-two offsets. */ /* Write the default pattern at each of the power-of-two offsets. */
for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
offset <<= 1) { offset <<= 1) {
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)offset, mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset,
DDR_PATTERN); DDR_PATTERN);
} }
/* Check for address bits stuck high. */ /* Check for address bits stuck high. */
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
DDR_ANTIPATTERN); DDR_ANTIPATTERN);
for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
offset <<= 1) { offset <<= 1) {
if (mmio_read_32(STM32MP1_DDR_BASE + (uint32_t)offset) != if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) !=
DDR_PATTERN) { DDR_PATTERN) {
return (uint32_t)(STM32MP1_DDR_BASE + offset); return (uint32_t)(STM32MP_DDR_BASE + offset);
} }
} }
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN);
/* Check for address bits stuck low or shorted. */ /* Check for address bits stuck low or shorted. */
for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U; for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U;
testoffset <<= 1) { testoffset <<= 1) {
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
DDR_ANTIPATTERN); DDR_ANTIPATTERN);
if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) { if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
return STM32MP1_DDR_BASE; return STM32MP_DDR_BASE;
} }
for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
offset <<= 1) { offset <<= 1) {
if ((mmio_read_32(STM32MP1_DDR_BASE + if ((mmio_read_32(STM32MP_DDR_BASE +
(uint32_t)offset) != DDR_PATTERN) && (uint32_t)offset) != DDR_PATTERN) &&
(offset != testoffset)) { (offset != testoffset)) {
return (uint32_t)(STM32MP1_DDR_BASE + offset); return (uint32_t)(STM32MP_DDR_BASE + offset);
} }
} }
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
DDR_PATTERN); DDR_PATTERN);
} }
...@@ -147,13 +144,13 @@ static uint32_t ddr_check_size(void) ...@@ -147,13 +144,13 @@ static uint32_t ddr_check_size(void)
{ {
uint32_t offset = sizeof(uint32_t); uint32_t offset = sizeof(uint32_t);
mmio_write_32(STM32MP1_DDR_BASE, DDR_PATTERN); mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
while (offset < STM32MP1_DDR_MAX_SIZE) { while (offset < STM32MP_DDR_MAX_SIZE) {
mmio_write_32(STM32MP1_DDR_BASE + offset, DDR_ANTIPATTERN); mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN);
dsb(); dsb();
if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) { if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
break; break;
} }
...@@ -171,7 +168,7 @@ static int stm32mp1_ddr_setup(void) ...@@ -171,7 +168,7 @@ static int stm32mp1_ddr_setup(void)
int ret; int ret;
struct stm32mp1_ddr_config config; struct stm32mp1_ddr_config config;
int node, len; int node, len;
uint32_t tamp_clk_off = 0, uret, idx; uint32_t uret, idx;
void *fdt; void *fdt;
#define PARAM(x, y) \ #define PARAM(x, y) \
...@@ -240,19 +237,6 @@ static int stm32mp1_ddr_setup(void) ...@@ -240,19 +237,6 @@ static int stm32mp1_ddr_setup(void)
} }
} }
if (!stm32mp1_clk_is_enabled(RTCAPB)) {
tamp_clk_off = 1;
if (stm32mp1_clk_enable(RTCAPB) != 0) {
return -EINVAL;
}
}
if (tamp_clk_off != 0U) {
if (stm32mp1_clk_disable(RTCAPB) != 0) {
return -EINVAL;
}
}
/* Disable axidcg clock gating during init */ /* Disable axidcg clock gating during init */
mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
...@@ -301,12 +285,12 @@ int stm32mp1_ddr_probe(void) ...@@ -301,12 +285,12 @@ int stm32mp1_ddr_probe(void)
VERBOSE("STM32MP DDR probe\n"); VERBOSE("STM32MP DDR probe\n");
priv->ctl = (struct stm32mp1_ddrctl *)DDRCTRL_BASE; priv->ctl = (struct stm32mp1_ddrctl *)stm32mp_ddrctrl_base();
priv->phy = (struct stm32mp1_ddrphy *)DDRPHYC_BASE; priv->phy = (struct stm32mp1_ddrphy *)stm32mp_ddrphyc_base();
priv->pwr = PWR_BASE; priv->pwr = stm32mp_pwr_base();
priv->rcc = RCC_BASE; priv->rcc = stm32mp_rcc_base();
priv->info.base = STM32MP1_DDR_BASE; priv->info.base = STM32MP_DDR_BASE;
priv->info.size = 0; priv->info.size = 0;
return stm32mp1_ddr_setup(); return stm32mp1_ddr_setup();
......
drivers/st/gpio/stm32_gpio.c
View file @ 37cdad2a
...@@ -15,8 +15,7 @@ ...@@ -15,8 +15,7 @@
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h> #include <common/debug.h>
#include <drivers/st/stm32_gpio.h> #include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp1_clk.h> #include <drivers/st/stm32mp_clkfunc.h>
#include <drivers/st/stm32mp1_clkfunc.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/utils_def.h> #include <lib/utils_def.h>
...@@ -208,7 +207,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, ...@@ -208,7 +207,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
assert(pin <= GPIO_PIN_MAX); assert(pin <= GPIO_PIN_MAX);
stm32mp1_clk_enable(clock); stm32mp_clk_enable(clock);
mmio_clrbits_32(base + GPIO_MODE_OFFSET, mmio_clrbits_32(base + GPIO_MODE_OFFSET,
((uint32_t)GPIO_MODE_MASK << (pin << 1))); ((uint32_t)GPIO_MODE_MASK << (pin << 1)));
...@@ -254,17 +253,17 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, ...@@ -254,17 +253,17 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank, VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
mmio_read_32(base + GPIO_AFRH_OFFSET)); mmio_read_32(base + GPIO_AFRH_OFFSET));
stm32mp1_clk_disable((unsigned long)clock); stm32mp_clk_disable(clock);
} }
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure) void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
{ {
uintptr_t base = stm32_get_gpio_bank_base(bank); uintptr_t base = stm32_get_gpio_bank_base(bank);
int clock = stm32_get_gpio_bank_clock(bank); unsigned long clock = stm32_get_gpio_bank_clock(bank);
assert(pin <= GPIO_PIN_MAX); assert(pin <= GPIO_PIN_MAX);
stm32mp1_clk_enable((unsigned long)clock); stm32mp_clk_enable(clock);
if (secure) { if (secure) {
mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
...@@ -272,5 +271,5 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure) ...@@ -272,5 +271,5 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
} }
stm32mp1_clk_disable((unsigned long)clock); stm32mp_clk_disable(clock);
} }
drivers/st/i2c/stm32_i2c.c
View file @ 37cdad2a
...@@ -8,10 +8,16 @@ ...@@ -8,10 +8,16 @@
#include <stdbool.h> #include <stdbool.h>
#include <stdlib.h> #include <stdlib.h>
#include <arch_helpers.h> #include <libfdt.h>
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/delay_timer.h> #include <drivers/delay_timer.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32_i2c.h> #include <drivers/st/stm32_i2c.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/utils.h>
/* STM32 I2C registers offsets */ /* STM32 I2C registers offsets */
#define I2C_CR1 0x00U #define I2C_CR1 0x00U
...@@ -26,50 +32,122 @@ ...@@ -26,50 +32,122 @@
#define I2C_RXDR 0x24U #define I2C_RXDR 0x24U
#define I2C_TXDR 0x28U #define I2C_TXDR 0x28U
#define MAX_DELAY 0xFFFFFFFFU #define TIMINGR_CLEAR_MASK 0xF0FFFFFFU
/* I2C TIMING clear register Mask */
#define TIMING_CLEAR_MASK 0xF0FFFFFFU
/* Timeout 25 ms */
#define I2C_TIMEOUT_BUSY 25U
#define MAX_NBYTE_SIZE 255U #define MAX_NBYTE_SIZE 255U
static int i2c_request_memory_write(struct i2c_handle_s *hi2c, #define I2C_NSEC_PER_SEC 1000000000L
uint16_t dev_addr, uint16_t mem_addr,
uint16_t mem_add_size, uint32_t timeout,
uint32_t tick_start);
static int i2c_request_memory_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size,
uint32_t timeout, uint32_t tick_start);
/* Private functions to handle flags during polling transfer */ /* I2C Timing hard-coded value, for I2C clock source is HSI at 64MHz */
static int i2c_wait_flag(struct i2c_handle_s *hi2c, uint32_t flag, #define I2C_TIMING 0x10D07DB5
uint8_t awaited_value, uint32_t timeout,
uint32_t tick_start); static void notif_i2c_timeout(struct i2c_handle_s *hi2c)
static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint32_t timeout, {
uint32_t tick_start); hi2c->i2c_err |= I2C_ERROR_TIMEOUT;
static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint32_t timeout, hi2c->i2c_mode = I2C_MODE_NONE;
uint32_t tick_start); hi2c->i2c_state = I2C_STATE_READY;
static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint32_t timeout, }
uint32_t tick_start);
/*
/* Private function to flush TXDR register */ * @brief Configure I2C Analog noise filter.
static void i2c_flush_txdr(struct i2c_handle_s *hi2c); * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C peripheral.
/* Private function to start, restart or stop a transfer */ * @param analog_filter: New state of the Analog filter
static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint16_t dev_addr, * @retval 0 if OK, negative value else
uint16_t size, uint32_t i2c_mode, */
uint32_t request); static int i2c_config_analog_filter(struct i2c_handle_s *hi2c,
uint32_t analog_filter)
{
if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) {
return -EBUSY;
}
hi2c->lock = 1;
hi2c->i2c_state = I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
/* Reset I2Cx ANOFF bit */
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_ANFOFF);
/* Set analog filter bit*/
mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR1, analog_filter);
/* Enable the selected I2C peripheral */
mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
hi2c->i2c_state = I2C_STATE_READY;
hi2c->lock = 0;
return 0;
}
/*
* @brief Get I2C setup information from the device tree and set pinctrl
* configuration.
* @param fdt: Pointer to the device tree
* @param node: I2C node offset
* @param init: Ref to the initialization configuration structure
* @retval 0 if OK, negative value else
*/
int stm32_i2c_get_setup_from_fdt(void *fdt, int node,
struct stm32_i2c_init_s *init)
{
const fdt32_t *cuint;
cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL);
if (cuint == NULL) {
init->rise_time = STM32_I2C_RISE_TIME_DEFAULT;
} else {
init->rise_time = fdt32_to_cpu(*cuint);
}
cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL);
if (cuint == NULL) {
init->fall_time = STM32_I2C_FALL_TIME_DEFAULT;
} else {
init->fall_time = fdt32_to_cpu(*cuint);
}
cuint = fdt_getprop(fdt, node, "clock-frequency", NULL);
if (cuint == NULL) {
init->speed_mode = STM32_I2C_SPEED_DEFAULT;
} else {
switch (fdt32_to_cpu(*cuint)) {
case STANDARD_RATE:
init->speed_mode = I2C_SPEED_STANDARD;
break;
case FAST_RATE:
init->speed_mode = I2C_SPEED_FAST;
break;
case FAST_PLUS_RATE:
init->speed_mode = I2C_SPEED_FAST_PLUS;
break;
default:
init->speed_mode = STM32_I2C_SPEED_DEFAULT;
break;
}
}
return dt_set_pinctrl_config(node);
}
/* /*
* @brief Initialize the I2C device. * @brief Initialize the I2C device.
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param init_data: Initialization configuration structure
* @retval 0 if OK, negative value else * @retval 0 if OK, negative value else
*/ */
int stm32_i2c_init(struct i2c_handle_s *hi2c) int stm32_i2c_init(struct i2c_handle_s *hi2c,
struct stm32_i2c_init_s *init_data)
{ {
int rc = 0;
uint32_t timing = I2C_TIMING;
if (hi2c == NULL) { if (hi2c == NULL) {
return -ENOENT; return -ENOENT;
} }
...@@ -80,34 +158,38 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c) ...@@ -80,34 +158,38 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c)
hi2c->i2c_state = I2C_STATE_BUSY; hi2c->i2c_state = I2C_STATE_BUSY;
stm32mp_clk_enable(hi2c->clock);
/* Disable the selected I2C peripheral */ /* Disable the selected I2C peripheral */
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE); mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
/* Configure I2Cx: Frequency range */ /* Configure I2Cx: Frequency range */
mmio_write_32(hi2c->i2c_base_addr + I2C_TIMINGR, mmio_write_32(hi2c->i2c_base_addr + I2C_TIMINGR,
hi2c->i2c_init.timing & TIMING_CLEAR_MASK); timing & TIMINGR_CLEAR_MASK);
/* Disable Own Address1 before set the Own Address1 configuration */ /* Disable Own Address1 before set the Own Address1 configuration */
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_OAR1, I2C_OAR1_OA1EN); mmio_clrbits_32(hi2c->i2c_base_addr + I2C_OAR1, I2C_OAR1_OA1EN);
/* Configure I2Cx: Own Address1 and ack own address1 mode */ /* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->i2c_init.addressing_mode == I2C_ADDRESSINGMODE_7BIT) { if (init_data->addressing_mode == I2C_ADDRESSINGMODE_7BIT) {
mmio_write_32(hi2c->i2c_base_addr + I2C_OAR1, mmio_write_32(hi2c->i2c_base_addr + I2C_OAR1,
I2C_OAR1_OA1EN | hi2c->i2c_init.own_address1); I2C_OAR1_OA1EN | init_data->own_address1);
} else { /* I2C_ADDRESSINGMODE_10BIT */ } else { /* I2C_ADDRESSINGMODE_10BIT */
mmio_write_32(hi2c->i2c_base_addr + I2C_OAR1, mmio_write_32(hi2c->i2c_base_addr + I2C_OAR1,
I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE |
hi2c->i2c_init.own_address1); init_data->own_address1);
} }
mmio_write_32(hi2c->i2c_base_addr + I2C_CR2, 0);
/* Configure I2Cx: Addressing Master mode */ /* Configure I2Cx: Addressing Master mode */
if (hi2c->i2c_init.addressing_mode == I2C_ADDRESSINGMODE_10BIT) { if (init_data->addressing_mode == I2C_ADDRESSINGMODE_10BIT) {
mmio_write_32(hi2c->i2c_base_addr + I2C_CR2, I2C_CR2_ADD10); mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_CR2_ADD10);
} }
/* /*
* Enable the AUTOEND by default, and enable NACK * Enable the AUTOEND by default, and enable NACK
* (should be disable only during Slave process) * (should be disabled only during Slave process).
*/ */
mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR2, mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR2,
I2C_CR2_AUTOEND | I2C_CR2_NACK); I2C_CR2_AUTOEND | I2C_CR2_NACK);
...@@ -117,14 +199,14 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c) ...@@ -117,14 +199,14 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c)
/* Configure I2Cx: Dual mode and Own Address2 */ /* Configure I2Cx: Dual mode and Own Address2 */
mmio_write_32(hi2c->i2c_base_addr + I2C_OAR2, mmio_write_32(hi2c->i2c_base_addr + I2C_OAR2,
hi2c->i2c_init.dual_address_mode | init_data->dual_address_mode |
hi2c->i2c_init.own_address2 | init_data->own_address2 |
(hi2c->i2c_init.own_address2_masks << 8)); (init_data->own_address2_masks << 8));
/* Configure I2Cx: Generalcall and NoStretch mode */ /* Configure I2Cx: Generalcall and NoStretch mode */
mmio_write_32(hi2c->i2c_base_addr + I2C_CR1, mmio_write_32(hi2c->i2c_base_addr + I2C_CR1,
hi2c->i2c_init.general_call_mode | init_data->general_call_mode |
hi2c->i2c_init.no_stretch_mode); init_data->no_stretch_mode);
/* Enable the selected I2C peripheral */ /* Enable the selected I2C peripheral */
mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE); mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
...@@ -133,366 +215,207 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c) ...@@ -133,366 +215,207 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c)
hi2c->i2c_state = I2C_STATE_READY; hi2c->i2c_state = I2C_STATE_READY;
hi2c->i2c_mode = I2C_MODE_NONE; hi2c->i2c_mode = I2C_MODE_NONE;
return 0; rc = i2c_config_analog_filter(hi2c, init_data->analog_filter ?
I2C_ANALOGFILTER_ENABLE :
I2C_ANALOGFILTER_DISABLE);
if (rc != 0) {
ERROR("Cannot initialize I2C analog filter (%d)\n", rc);
stm32mp_clk_disable(hi2c->clock);
return rc;
}
stm32mp_clk_disable(hi2c->clock);
return rc;
} }
/* /*
* @brief Write an amount of data in blocking mode to a specific memory address * @brief I2C Tx data register flush process.
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains * @param hi2c: I2C handle
* the configuration information for the specified I2C. * @retval None
* @param dev_addr: Target device address
* @param mem_addr: Internal memory address
* @param mem_add_size: size of internal memory address
* @param p_data: Pointer to data buffer
* @param size: Amount of data to be sent
* @param timeout: timeout duration
* @retval 0 if OK, negative value else
*/ */
int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr, static void i2c_flush_txdr(struct i2c_handle_s *hi2c)
uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout)
{ {
uint32_t tickstart; /*
* If a pending TXIS flag is set,
if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) { * write a dummy data in TXDR to clear it.
return -EBUSY; */
if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_TXIS) !=
0U) {
mmio_write_32(hi2c->i2c_base_addr + I2C_TXDR, 0);
} }
if ((p_data == NULL) || (size == 0U)) { /* Flush TX register if not empty */
return -EINVAL; if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_TXE) ==
0U) {
mmio_setbits_32(hi2c->i2c_base_addr + I2C_ISR,
I2C_FLAG_TXE);
} }
}
hi2c->lock = 1; /*
* @brief This function handles I2C Communication timeout.
tickstart = (uint32_t)read_cntpct_el0(); * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C.
* @param flag: Specifies the I2C flag to check
* @param awaited_value: The awaited bit value for the flag (0 or 1)
* @param timeout_ref: Reference to target timeout
* @retval 0 if OK, negative value else
*/
static int i2c_wait_flag(struct i2c_handle_s *hi2c, uint32_t flag,
uint8_t awaited_value, uint64_t timeout_ref)
{
for ( ; ; ) {
uint32_t isr = mmio_read_32(hi2c->i2c_base_addr + I2C_ISR);
if (i2c_wait_flag(hi2c, I2C_FLAG_BUSY, 1, I2C_TIMEOUT_BUSY, if (!!(isr & flag) != !!awaited_value) {
tickstart) != 0) { return 0;
return -EIO; }
}
hi2c->i2c_state = I2C_STATE_BUSY_TX; if (timeout_elapsed(timeout_ref)) {
hi2c->i2c_mode = I2C_MODE_MEM; notif_i2c_timeout(hi2c);
hi2c->i2c_err = I2C_ERROR_NONE; hi2c->lock = 0;
hi2c->p_buff = p_data; return -EIO;
hi2c->xfer_count = size; }
}
}
/* Send Slave Address and Memory Address */ /*
if (i2c_request_memory_write(hi2c, dev_addr, mem_addr, mem_add_size, * @brief This function handles Acknowledge failed detection during
timeout, tickstart) != 0) { * an I2C Communication.
hi2c->lock = 0; * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
return -EIO; * the configuration information for the specified I2C.
* @param timeout_ref: Reference to target timeout
* @retval 0 if OK, negative value else
*/
static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
{
if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_AF) == 0U) {
return 0;
} }
/* /*
* Set NBYTES to write and reload * Wait until STOP Flag is reset.
* if hi2c->xfer_count > MAX_NBYTE_SIZE * AutoEnd should be initiate after AF.
*/ */
if (hi2c->xfer_count > MAX_NBYTE_SIZE) { while ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
hi2c->xfer_size = MAX_NBYTE_SIZE; I2C_FLAG_STOPF) == 0U) {
i2c_transfer_config(hi2c, dev_addr, hi2c->xfer_size, if (timeout_elapsed(timeout_ref)) {
I2C_RELOAD_MODE, I2C_NO_STARTSTOP); notif_i2c_timeout(hi2c);
} else { hi2c->lock = 0;
hi2c->xfer_size = hi2c->xfer_count;
i2c_transfer_config(hi2c, dev_addr, hi2c->xfer_size,
I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
do {
if (i2c_wait_txis(hi2c, timeout, tickstart) != 0) {
return -EIO; return -EIO;
} }
mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR, *hi2c->p_buff);
hi2c->p_buff++;
hi2c->xfer_count--;
hi2c->xfer_size--;
if ((hi2c->xfer_count != 0U) && (hi2c->xfer_size == 0U)) {
/* Wait until TCR flag is set */
if (i2c_wait_flag(hi2c, I2C_FLAG_TCR, 0, timeout,
tickstart) != 0) {
return -EIO;
}
if (hi2c->xfer_count > MAX_NBYTE_SIZE) {
hi2c->xfer_size = MAX_NBYTE_SIZE;
i2c_transfer_config(hi2c, dev_addr,
hi2c->xfer_size,
I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
} else {
hi2c->xfer_size = hi2c->xfer_count;
i2c_transfer_config(hi2c, dev_addr,
hi2c->xfer_size,
I2C_AUTOEND_MODE,
I2C_NO_STARTSTOP);
}
}
} while (hi2c->xfer_count > 0U);
/*
* No need to Check TC flag, with AUTOEND mode the stop
* is automatically generated.
* Wait until STOPF flag is reset.
*/
if (i2c_wait_stop(hi2c, timeout, tickstart) != 0) {
return -EIO;
} }
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_AF);
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF); mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
i2c_flush_txdr(hi2c);
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2); mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2);
hi2c->i2c_err |= I2C_ERROR_AF;
hi2c->i2c_state = I2C_STATE_READY; hi2c->i2c_state = I2C_STATE_READY;
hi2c->i2c_mode = I2C_MODE_NONE; hi2c->i2c_mode = I2C_MODE_NONE;
hi2c->lock = 0; hi2c->lock = 0;
return 0; return -EIO;
} }
/* /*
* @brief Read an amount of data in blocking mode from a specific memory * @brief This function handles I2C Communication timeout for specific usage
* address * of TXIS flag.
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param dev_addr: Target device address * @param timeout_ref: Reference to target timeout
* @param mem_addr: Internal memory address
* @param mem_add_size: size of internal memory address
* @param p_data: Pointer to data buffer
* @param size: Amount of data to be sent
* @param timeout: timeout duration
* @retval 0 if OK, negative value else * @retval 0 if OK, negative value else
*/ */
int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr, static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout)
{ {
uint32_t tickstart; while ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
I2C_FLAG_TXIS) == 0U) {
if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) { if (i2c_ack_failed(hi2c, timeout_ref) != 0) {
return -EBUSY;
}
if ((p_data == NULL) || (size == 0U)) {
return -EINVAL;
}
hi2c->lock = 1;
tickstart = (uint32_t)read_cntpct_el0();
if (i2c_wait_flag(hi2c, I2C_FLAG_BUSY, 1, I2C_TIMEOUT_BUSY,
tickstart) != 0) {
return -EIO;
}
hi2c->i2c_state = I2C_STATE_BUSY_RX;
hi2c->i2c_mode = I2C_MODE_MEM;
hi2c->i2c_err = I2C_ERROR_NONE;
hi2c->p_buff = p_data;
hi2c->xfer_count = size;
/* Send Slave Address and Memory Address */
if (i2c_request_memory_read(hi2c, dev_addr, mem_addr, mem_add_size,
timeout, tickstart) != 0) {
hi2c->lock = 0;
return -EIO;
}
/*
* Send Slave Address.
* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE
* and generate RESTART.
*/
if (hi2c->xfer_count > MAX_NBYTE_SIZE) {
hi2c->xfer_size = MAX_NBYTE_SIZE;
i2c_transfer_config(hi2c, dev_addr, hi2c->xfer_size,
I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
} else {
hi2c->xfer_size = hi2c->xfer_count;
i2c_transfer_config(hi2c, dev_addr, hi2c->xfer_size,
I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
do {
if (i2c_wait_flag(hi2c, I2C_FLAG_RXNE, 0, timeout,
tickstart) != 0) {
return -EIO; return -EIO;
} }
*hi2c->p_buff = mmio_read_8(hi2c->i2c_base_addr + I2C_RXDR); if (timeout_elapsed(timeout_ref)) {
hi2c->p_buff++; notif_i2c_timeout(hi2c);
hi2c->xfer_size--; hi2c->lock = 0;
hi2c->xfer_count--;
if ((hi2c->xfer_count != 0U) && (hi2c->xfer_size == 0U)) {
if (i2c_wait_flag(hi2c, I2C_FLAG_TCR, 0, timeout,
tickstart) != 0) {
return -EIO;
}
if (hi2c->xfer_count > MAX_NBYTE_SIZE) { return -EIO;
hi2c->xfer_size = MAX_NBYTE_SIZE;
i2c_transfer_config(hi2c, dev_addr,
hi2c->xfer_size,
I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
} else {
hi2c->xfer_size = hi2c->xfer_count;
i2c_transfer_config(hi2c, dev_addr,
hi2c->xfer_size,
I2C_AUTOEND_MODE,
I2C_NO_STARTSTOP);
}
} }
} while (hi2c->xfer_count > 0U);
/*
* No need to Check TC flag, with AUTOEND mode the stop
* is automatically generated
* Wait until STOPF flag is reset
*/
if (i2c_wait_stop(hi2c, timeout, tickstart) != 0) {
return -EIO;
} }
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2);
hi2c->i2c_state = I2C_STATE_READY;
hi2c->i2c_mode = I2C_MODE_NONE;
hi2c->lock = 0;
return 0; return 0;
} }
/* /*
* @brief Checks if target device is ready for communication. * @brief This function handles I2C Communication timeout for specific
* @note This function is used with Memory devices * usage of STOP flag.
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param dev_addr: Target device address * @param timeout_ref: Reference to target timeout
* @param trials: Number of trials
* @param timeout: timeout duration
* @retval 0 if OK, negative value else * @retval 0 if OK, negative value else
*/ */
int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
uint16_t dev_addr, uint32_t trials,
uint32_t timeout)
{ {
uint32_t i2c_trials = 0U; while ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
I2C_FLAG_STOPF) == 0U) {
if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) { if (i2c_ack_failed(hi2c, timeout_ref) != 0) {
return -EBUSY; return -EIO;
} }
if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_BUSY) !=
0U) {
return -EBUSY;
}
hi2c->lock = 1;
hi2c->i2c_state = I2C_STATE_BUSY;
hi2c->i2c_err = I2C_ERROR_NONE;
do {
uint32_t tickstart;
/* Generate Start */
if (hi2c->i2c_init.addressing_mode == I2C_ADDRESSINGMODE_7BIT) {
mmio_write_32(hi2c->i2c_base_addr + I2C_CR2,
(((uint32_t)dev_addr & I2C_CR2_SADD) |
I2C_CR2_START | I2C_CR2_AUTOEND) &
~I2C_CR2_RD_WRN);
} else {
mmio_write_32(hi2c->i2c_base_addr + I2C_CR2,
(((uint32_t)dev_addr & I2C_CR2_SADD) |
I2C_CR2_START | I2C_CR2_ADD10) &
~I2C_CR2_RD_WRN);
}
/*
* No need to Check TC flag, with AUTOEND mode the stop
* is automatically generated
* Wait until STOPF flag is set or a NACK flag is set
*/
tickstart = (uint32_t)read_cntpct_el0();
while (((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
(I2C_FLAG_STOPF | I2C_FLAG_AF)) == 0U) &&
(hi2c->i2c_state != I2C_STATE_TIMEOUT)) {
if (timeout != MAX_DELAY) {
if ((((uint32_t)read_cntpct_el0() - tickstart) >
timeout) || (timeout == 0U)) {
hi2c->i2c_state = I2C_STATE_READY;
hi2c->i2c_err |=
I2C_ERROR_TIMEOUT;
hi2c->lock = 0;
return -EIO;
}
}
}
/* Check if the NACKF flag has not been set */
if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
I2C_FLAG_AF) == 0U) {
if (i2c_wait_flag(hi2c, I2C_FLAG_STOPF, 0, timeout,
tickstart) != 0) {
return -EIO;
}
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR,
I2C_FLAG_STOPF);
hi2c->i2c_state = I2C_STATE_READY;
if (timeout_elapsed(timeout_ref)) {
notif_i2c_timeout(hi2c);
hi2c->lock = 0; hi2c->lock = 0;
return 0;
}
if (i2c_wait_flag(hi2c, I2C_FLAG_STOPF, 0, timeout,
tickstart) != 0) {
return -EIO; return -EIO;
} }
}
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_AF); return 0;
}
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
if (i2c_trials == trials) {
mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR2,
I2C_CR2_STOP);
if (i2c_wait_flag(hi2c, I2C_FLAG_STOPF, 0, timeout,
tickstart) != 0) {
return -EIO;
}
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR,
I2C_FLAG_STOPF);
}
i2c_trials++;
} while (i2c_trials < trials);
hi2c->i2c_state = I2C_STATE_READY; /*
* @brief Handles I2Cx communication when starting transfer or during transfer
* (TC or TCR flag are set).
* @param hi2c: I2C handle
* @param dev_addr: Specifies the slave address to be programmed
* @param size: Specifies the number of bytes to be programmed.
* This parameter must be a value between 0 and 255.
* @param i2c_mode: New state of the I2C START condition generation.
* This parameter can be one of the following values:
* @arg @ref I2C_RELOAD_MODE: Enable Reload mode.
* @arg @ref I2C_AUTOEND_MODE: Enable Automatic end mode.
* @arg @ref I2C_SOFTEND_MODE: Enable Software end mode.
* @param request: New state of the I2C START condition generation.
* This parameter can be one of the following values:
* @arg @ref I2C_NO_STARTSTOP: Don't Generate stop and start condition.
* @arg @ref I2C_GENERATE_STOP: Generate stop condition
* (size should be set to 0).
* @arg @ref I2C_GENERATE_START_READ: Generate Restart for read request.
* @arg @ref I2C_GENERATE_START_WRITE: Generate Restart for write request.
* @retval None
*/
static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t size, uint32_t i2c_mode,
uint32_t request)
{
uint32_t clr_value, set_value;
hi2c->i2c_err |= I2C_ERROR_TIMEOUT; clr_value = (I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD |
I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP) |
(I2C_CR2_RD_WRN & (request >> (31U - I2C_CR2_RD_WRN_OFFSET)));
hi2c->lock = 0; set_value = ((uint32_t)dev_addr & I2C_CR2_SADD) |
(((uint32_t)size << I2C_CR2_NBYTES_OFFSET) & I2C_CR2_NBYTES) |
i2c_mode | request;
return -EIO; mmio_clrsetbits_32(hi2c->i2c_base_addr + I2C_CR2, clr_value, set_value);
} }
/* /*
...@@ -502,20 +425,18 @@ int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, ...@@ -502,20 +425,18 @@ int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c,
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param dev_addr: Target device address * @param dev_addr: Target device address
* @param mem_addr: Internal memory address * @param mem_addr: Internal memory address
* @param mem_add_size: size of internal memory address * @param mem_add_size: Size of internal memory address
* @param timeout: timeout duration * @param timeout_ref: Reference to target timeout
* @param tick_start Tick start value
* @retval 0 if OK, negative value else * @retval 0 if OK, negative value else
*/ */
static int i2c_request_memory_write(struct i2c_handle_s *hi2c, static int i2c_request_memory_write(struct i2c_handle_s *hi2c,
uint16_t dev_addr, uint16_t mem_addr, uint16_t dev_addr, uint16_t mem_addr,
uint16_t mem_add_size, uint32_t timeout, uint16_t mem_add_size, uint64_t timeout_ref)
uint32_t tick_start)
{ {
i2c_transfer_config(hi2c, dev_addr, mem_add_size, I2C_RELOAD_MODE, i2c_transfer_config(hi2c, dev_addr, mem_add_size, I2C_RELOAD_MODE,
I2C_GENERATE_START_WRITE); I2C_GENERATE_START_WRITE);
if (i2c_wait_txis(hi2c, timeout, tick_start) != 0) { if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
return -EIO; return -EIO;
} }
...@@ -528,8 +449,7 @@ static int i2c_request_memory_write(struct i2c_handle_s *hi2c, ...@@ -528,8 +449,7 @@ static int i2c_request_memory_write(struct i2c_handle_s *hi2c,
mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR, mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR,
(uint8_t)((mem_addr & 0xFF00U) >> 8)); (uint8_t)((mem_addr & 0xFF00U) >> 8));
/* Wait until TXIS flag is set */ if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
if (i2c_wait_txis(hi2c, timeout, tick_start) != 0) {
return -EIO; return -EIO;
} }
...@@ -538,8 +458,7 @@ static int i2c_request_memory_write(struct i2c_handle_s *hi2c, ...@@ -538,8 +458,7 @@ static int i2c_request_memory_write(struct i2c_handle_s *hi2c,
(uint8_t)(mem_addr & 0x00FFU)); (uint8_t)(mem_addr & 0x00FFU));
} }
if (i2c_wait_flag(hi2c, I2C_FLAG_TCR, 0, timeout, tick_start) != if (i2c_wait_flag(hi2c, I2C_FLAG_TCR, 0, timeout_ref) != 0) {
0) {
return -EIO; return -EIO;
} }
...@@ -553,19 +472,18 @@ static int i2c_request_memory_write(struct i2c_handle_s *hi2c, ...@@ -553,19 +472,18 @@ static int i2c_request_memory_write(struct i2c_handle_s *hi2c,
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param dev_addr: Target device address * @param dev_addr: Target device address
* @param mem_addr: Internal memory address * @param mem_addr: Internal memory address
* @param mem_add_size: size of internal memory address * @param mem_add_size: Size of internal memory address
* @param timeout: timeout duration * @param timeout_ref: Reference to target timeout
* @param tick_start Tick start value
* @retval 0 if OK, negative value else * @retval 0 if OK, negative value else
*/ */
static int i2c_request_memory_read(struct i2c_handle_s *hi2c, uint16_t dev_addr, static int i2c_request_memory_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size, uint16_t mem_addr, uint16_t mem_add_size,
uint32_t timeout, uint32_t tick_start) uint64_t timeout_ref)
{ {
i2c_transfer_config(hi2c, dev_addr, mem_add_size, I2C_SOFTEND_MODE, i2c_transfer_config(hi2c, dev_addr, mem_add_size, I2C_SOFTEND_MODE,
I2C_GENERATE_START_WRITE); I2C_GENERATE_START_WRITE);
if (i2c_wait_txis(hi2c, timeout, tick_start) != 0) { if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
return -EIO; return -EIO;
} }
...@@ -578,8 +496,7 @@ static int i2c_request_memory_read(struct i2c_handle_s *hi2c, uint16_t dev_addr, ...@@ -578,8 +496,7 @@ static int i2c_request_memory_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR, mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR,
(uint8_t)((mem_addr & 0xFF00U) >> 8)); (uint8_t)((mem_addr & 0xFF00U) >> 8));
/* Wait until TXIS flag is set */ if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
if (i2c_wait_txis(hi2c, timeout, tick_start) != 0) {
return -EIO; return -EIO;
} }
...@@ -588,265 +505,477 @@ static int i2c_request_memory_read(struct i2c_handle_s *hi2c, uint16_t dev_addr, ...@@ -588,265 +505,477 @@ static int i2c_request_memory_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
(uint8_t)(mem_addr & 0x00FFU)); (uint8_t)(mem_addr & 0x00FFU));
} }
if (i2c_wait_flag(hi2c, I2C_FLAG_TC, 0, timeout, tick_start) != 0) { if (i2c_wait_flag(hi2c, I2C_FLAG_TC, 0, timeout_ref) != 0) {
return -EIO; return -EIO;
} }
return 0; return 0;
} }
/* /*
* @brief I2C Tx data register flush process. * @brief Generic function to write an amount of data in blocking mode
* @param hi2c: I2C handle. * (for Memory Mode and Master Mode)
* @retval None * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C.
* @param dev_addr: Target device address
* @param mem_addr: Internal memory address (if Memory Mode)
* @param mem_add_size: Size of internal memory address (if Memory Mode)
* @param p_data: Pointer to data buffer
* @param size: Amount of data to be sent
* @param timeout_ms: Timeout duration in milliseconds
* @param mode: Communication mode
* @retval 0 if OK, negative value else
*/ */
static void i2c_flush_txdr(struct i2c_handle_s *hi2c) static int i2c_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout_ms,
enum i2c_mode_e mode)
{ {
uint64_t timeout_ref;
int rc = -EIO;
uint8_t *p_buff = p_data;
uint32_t xfer_size;
uint32_t xfer_count = size;
if ((mode != I2C_MODE_MASTER) && (mode != I2C_MODE_MEM)) {
return -1;
}
if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) {
return -EBUSY;
}
if ((p_data == NULL) || (size == 0U)) {
return -EINVAL;
}
stm32mp_clk_enable(hi2c->clock);
hi2c->lock = 1;
timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000);
if (i2c_wait_flag(hi2c, I2C_FLAG_BUSY, 1, timeout_ref) != 0) {
goto bail;
}
hi2c->i2c_state = I2C_STATE_BUSY_TX;
hi2c->i2c_mode = mode;
hi2c->i2c_err = I2C_ERROR_NONE;
timeout_ref = timeout_init_us(timeout_ms * 1000);
if (mode == I2C_MODE_MEM) {
/* In Memory Mode, Send Slave Address and Memory Address */
if (i2c_request_memory_write(hi2c, dev_addr, mem_addr,
mem_add_size, timeout_ref) != 0) {
goto bail;
}
if (xfer_count > MAX_NBYTE_SIZE) {
xfer_size = MAX_NBYTE_SIZE;
i2c_transfer_config(hi2c, dev_addr, xfer_size,
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
} else {
xfer_size = xfer_count;
i2c_transfer_config(hi2c, dev_addr, xfer_size,
I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
} else {
/* In Master Mode, Send Slave Address */
if (xfer_count > MAX_NBYTE_SIZE) {
xfer_size = MAX_NBYTE_SIZE;
i2c_transfer_config(hi2c, dev_addr, xfer_size,
I2C_RELOAD_MODE,
I2C_GENERATE_START_WRITE);
} else {
xfer_size = xfer_count;
i2c_transfer_config(hi2c, dev_addr, xfer_size,
I2C_AUTOEND_MODE,
I2C_GENERATE_START_WRITE);
}
}
do {
if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
goto bail;
}
mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR, *p_buff);
p_buff++;
xfer_count--;
xfer_size--;
if ((xfer_count != 0U) && (xfer_size == 0U)) {
/* Wait until TCR flag is set */
if (i2c_wait_flag(hi2c, I2C_FLAG_TCR, 0,
timeout_ref) != 0) {
goto bail;
}
if (xfer_count > MAX_NBYTE_SIZE) {
xfer_size = MAX_NBYTE_SIZE;
i2c_transfer_config(hi2c, dev_addr,
xfer_size,
I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
} else {
xfer_size = xfer_count;
i2c_transfer_config(hi2c, dev_addr,
xfer_size,
I2C_AUTOEND_MODE,
I2C_NO_STARTSTOP);
}
}
} while (xfer_count > 0U);
/* /*
* If a pending TXIS flag is set, * No need to Check TC flag, with AUTOEND mode the stop
* write a dummy data in TXDR to clear it. * is automatically generated.
* Wait until STOPF flag is reset.
*/ */
if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_TXIS) != if (i2c_wait_stop(hi2c, timeout_ref) != 0) {
0U) { goto bail;
mmio_write_32(hi2c->i2c_base_addr + I2C_TXDR, 0);
} }
/* Flush TX register if not empty */ mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_TXE) ==
0U) { mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2);
mmio_setbits_32(hi2c->i2c_base_addr + I2C_ISR,
I2C_FLAG_TXE); hi2c->i2c_state = I2C_STATE_READY;
} hi2c->i2c_mode = I2C_MODE_NONE;
rc = 0;
bail:
hi2c->lock = 0;
stm32mp_clk_disable(hi2c->clock);
return rc;
} }
/* /*
* @brief This function handles I2C Communication timeout. * @brief Write an amount of data in blocking mode to a specific memory
* address.
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param flag: Specifies the I2C flag to check. * @param dev_addr: Target device address
* @param awaited_value: The awaited bit value for the flag (0 or 1). * @param mem_addr: Internal memory address
* @param timeout: timeout duration * @param mem_add_size: Size of internal memory address
* @param tick_start: Tick start value * @param p_data: Pointer to data buffer
* @param size: Amount of data to be sent
* @param timeout_ms: Timeout duration in milliseconds
* @retval 0 if OK, negative value else * @retval 0 if OK, negative value else
*/ */
static int i2c_wait_flag(struct i2c_handle_s *hi2c, uint32_t flag, int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint8_t awaited_value, uint32_t timeout, uint16_t mem_addr, uint16_t mem_add_size,
uint32_t tick_start) uint8_t *p_data, uint16_t size, uint32_t timeout_ms)
{ {
uint8_t flag_check; return i2c_write(hi2c, dev_addr, mem_addr, mem_add_size,
p_data, size, timeout_ms, I2C_MODE_MEM);
do {
flag_check = ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
flag) == flag) ? 1U : 0U;
if (timeout != MAX_DELAY) {
if ((((uint32_t)read_cntpct_el0() - tick_start) >
timeout) || (timeout == 0U)) {
hi2c->i2c_err |= I2C_ERROR_TIMEOUT;
hi2c->i2c_state = I2C_STATE_READY;
hi2c->i2c_mode = I2C_MODE_NONE;
hi2c->lock = 0;
return -EIO;
}
}
} while (flag_check == awaited_value);
return 0;
} }
/* /*
* @brief This function handles I2C Communication timeout for specific usage * @brief Transmits in master mode an amount of data in blocking mode.
* of TXIS flag.
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param timeout: timeout duration * @param dev_addr: Target device address
* @param tick_start: Tick start value * @param p_data: Pointer to data buffer
* @param size: Amount of data to be sent
* @param timeout_ms: Timeout duration in milliseconds
* @retval 0 if OK, negative value else * @retval 0 if OK, negative value else
*/ */
static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint32_t timeout, int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t tick_start) uint8_t *p_data, uint16_t size,
uint32_t timeout_ms)
{ {
while ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & return i2c_write(hi2c, dev_addr, 0, 0,
I2C_FLAG_TXIS) == 0U) { p_data, size, timeout_ms, I2C_MODE_MASTER);
if (i2c_ack_failed(hi2c, timeout, tick_start) != 0) {
return -EIO;
}
if (timeout != MAX_DELAY) {
if ((((uint32_t)read_cntpct_el0() - tick_start) >
timeout) || (timeout == 0U)) {
hi2c->i2c_err |= I2C_ERROR_TIMEOUT;
hi2c->i2c_state = I2C_STATE_READY;
hi2c->i2c_mode = I2C_MODE_NONE;
hi2c->lock = 0;
return -EIO;
}
}
}
return 0;
} }
/* /*
* @brief This function handles I2C Communication timeout for specific * @brief Generic function to read an amount of data in blocking mode
* usage of STOP flag. * (for Memory Mode and Master Mode)
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param timeout: timeout duration * @param dev_addr: Target device address
* @param tick_start: Tick start value * @param mem_addr: Internal memory address (if Memory Mode)
* @param mem_add_size: Size of internal memory address (if Memory Mode)
* @param p_data: Pointer to data buffer
* @param size: Amount of data to be sent
* @param timeout_ms: Timeout duration in milliseconds
* @param mode: Communication mode
* @retval 0 if OK, negative value else * @retval 0 if OK, negative value else
*/ */
static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint32_t timeout, static int i2c_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t tick_start) uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout_ms,
enum i2c_mode_e mode)
{ {
while ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & uint64_t timeout_ref;
I2C_FLAG_STOPF) == 0U) { int rc = -EIO;
if (i2c_ack_failed(hi2c, timeout, tick_start) != 0) { uint8_t *p_buff = p_data;
return -EIO; uint32_t xfer_count = size;
} uint32_t xfer_size;
if ((mode != I2C_MODE_MASTER) && (mode != I2C_MODE_MEM)) {
return -1;
}
if ((((uint32_t)read_cntpct_el0() - tick_start) > timeout) || if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) {
(timeout == 0U)) { return -EBUSY;
hi2c->i2c_err |= I2C_ERROR_TIMEOUT; }
hi2c->i2c_state = I2C_STATE_READY;
hi2c->i2c_mode = I2C_MODE_NONE;
hi2c->lock = 0; if ((p_data == NULL) || (size == 0U)) {
return -EINVAL;
}
return -EIO; stm32mp_clk_enable(hi2c->clock);
}
hi2c->lock = 1;
timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000);
if (i2c_wait_flag(hi2c, I2C_FLAG_BUSY, 1, timeout_ref) != 0) {
goto bail;
} }
return 0; hi2c->i2c_state = I2C_STATE_BUSY_RX;
} hi2c->i2c_mode = mode;
hi2c->i2c_err = I2C_ERROR_NONE;
/* if (mode == I2C_MODE_MEM) {
* @brief This function handles Acknowledge failed detection during /* Send Memory Address */
* an I2C Communication. if (i2c_request_memory_read(hi2c, dev_addr, mem_addr,
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains mem_add_size, timeout_ref) != 0) {
* the configuration information for the specified I2C. goto bail;
* @param timeout: timeout duration }
* @param tick_start: Tick start value
* @retval 0 if OK, negative value else
*/
static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint32_t timeout,
uint32_t tick_start)
{
if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_AF) == 0U) {
return 0;
} }
/* /*
* Wait until STOP Flag is reset. * Send Slave Address.
* AutoEnd should be initiate after AF. * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE
* and generate RESTART.
*/ */
while ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & if (xfer_count > MAX_NBYTE_SIZE) {
I2C_FLAG_STOPF) == 0U) { xfer_size = MAX_NBYTE_SIZE;
if (timeout != MAX_DELAY) { i2c_transfer_config(hi2c, dev_addr, xfer_size,
if ((((uint32_t)read_cntpct_el0() - tick_start) > I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
timeout) || (timeout == 0U)) { } else {
hi2c->i2c_err |= I2C_ERROR_TIMEOUT; xfer_size = xfer_count;
hi2c->i2c_state = I2C_STATE_READY; i2c_transfer_config(hi2c, dev_addr, xfer_size,
hi2c->i2c_mode = I2C_MODE_NONE; I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
do {
if (i2c_wait_flag(hi2c, I2C_FLAG_RXNE, 0, timeout_ref) != 0) {
goto bail;
}
hi2c->lock = 0; *p_buff = mmio_read_8(hi2c->i2c_base_addr + I2C_RXDR);
p_buff++;
xfer_size--;
xfer_count--;
return -EIO; if ((xfer_count != 0U) && (xfer_size == 0U)) {
if (i2c_wait_flag(hi2c, I2C_FLAG_TCR, 0,
timeout_ref) != 0) {
goto bail;
}
if (xfer_count > MAX_NBYTE_SIZE) {
xfer_size = MAX_NBYTE_SIZE;
i2c_transfer_config(hi2c, dev_addr,
xfer_size,
I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
} else {
xfer_size = xfer_count;
i2c_transfer_config(hi2c, dev_addr,
xfer_size,
I2C_AUTOEND_MODE,
I2C_NO_STARTSTOP);
} }
} }
} } while (xfer_count > 0U);
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_AF); /*
* No need to Check TC flag, with AUTOEND mode the stop
* is automatically generated.
* Wait until STOPF flag is reset.
*/
if (i2c_wait_stop(hi2c, timeout_ref) != 0) {
goto bail;
}
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF); mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
i2c_flush_txdr(hi2c);
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2); mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2);
hi2c->i2c_err |= I2C_ERROR_AF;
hi2c->i2c_state = I2C_STATE_READY; hi2c->i2c_state = I2C_STATE_READY;
hi2c->i2c_mode = I2C_MODE_NONE; hi2c->i2c_mode = I2C_MODE_NONE;
rc = 0;
bail:
hi2c->lock = 0; hi2c->lock = 0;
stm32mp_clk_disable(hi2c->clock);
return -EIO; return rc;
} }
/* /*
* @brief Handles I2Cx communication when starting transfer or during transfer * @brief Read an amount of data in blocking mode from a specific memory
* (TC or TCR flag are set). * address.
* @param hi2c: I2C handle. * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* @param dev_addr: Specifies the slave address to be programmed. * the configuration information for the specified I2C.
* @param size: Specifies the number of bytes to be programmed. * @param dev_addr: Target device address
* This parameter must be a value between 0 and 255. * @param mem_addr: Internal memory address
* @param i2c_mode: New state of the I2C START condition generation. * @param mem_add_size: Size of internal memory address
* This parameter can be one of the following values: * @param p_data: Pointer to data buffer
* @arg @ref I2C_RELOAD_MODE: Enable Reload mode . * @param size: Amount of data to be sent
* @arg @ref I2C_AUTOEND_MODE: Enable Automatic end mode. * @param timeout_ms: Timeout duration in milliseconds
* @arg @ref I2C_SOFTEND_MODE: Enable Software end mode. * @retval 0 if OK, negative value else
* @param request: New state of the I2C START condition generation.
* This parameter can be one of the following values:
* @arg @ref I2C_NO_STARTSTOP: Don't Generate stop and start condition.
* @arg @ref I2C_GENERATE_STOP: Generate stop condition
* (size should be set to 0).
* @arg @ref I2C_GENERATE_START_READ: Generate Restart for read request.
* @arg @ref I2C_GENERATE_START_WRITE: Generate Restart for write request.
* @retval None
*/ */
static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint16_t dev_addr, int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t size, uint32_t i2c_mode, uint16_t mem_addr, uint16_t mem_add_size,
uint32_t request) uint8_t *p_data, uint16_t size, uint32_t timeout_ms)
{ {
uint32_t clr_value, set_value; return i2c_read(hi2c, dev_addr, mem_addr, mem_add_size,
p_data, size, timeout_ms, I2C_MODE_MEM);
clr_value = (I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD |
I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP) |
(I2C_CR2_RD_WRN & (request >> (31U - I2C_CR2_RD_WRN_OFFSET)));
set_value = ((uint32_t)dev_addr & I2C_CR2_SADD) |
(((uint32_t)size << I2C_CR2_NBYTES_OFFSET) & I2C_CR2_NBYTES) |
i2c_mode | request;
mmio_clrsetbits_32(hi2c->i2c_base_addr + I2C_CR2, clr_value, set_value);
} }
/* /*
* @brief Configure I2C Analog noise filter. * @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2Cx peripheral * the configuration information for the specified I2C.
* @param analog_filter: New state of the Analog filter. * @param dev_addr: Target device address
* @param p_data: Pointer to data buffer
* @param size: Amount of data to be sent
* @param timeout_ms: Timeout duration in milliseconds
* @retval 0 if OK, negative value else * @retval 0 if OK, negative value else
*/ */
int stm32_i2c_config_analog_filter(struct i2c_handle_s *hi2c, int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t analog_filter) uint8_t *p_data, uint16_t size,
uint32_t timeout_ms)
{
return i2c_read(hi2c, dev_addr, 0, 0,
p_data, size, timeout_ms, I2C_MODE_MASTER);
}
/*
* @brief Checks if target device is ready for communication.
* @note This function is used with Memory devices
* @param hi2c: Pointer to a struct i2c_handle_s structure that contains
* the configuration information for the specified I2C.
* @param dev_addr: Target device address
* @param trials: Number of trials
* @param timeout_ms: Timeout duration in milliseconds
* @retval True if device is ready, false else
*/
bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c,
uint16_t dev_addr, uint32_t trials,
uint32_t timeout_ms)
{ {
uint32_t i2c_trials = 0U;
bool rc = false;
if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) { if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) {
return -EBUSY; return rc;
} }
stm32mp_clk_enable(hi2c->clock);
hi2c->lock = 1; hi2c->lock = 1;
hi2c->i2c_mode = I2C_MODE_NONE;
if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_BUSY) !=
0U) {
goto bail;
}
hi2c->i2c_state = I2C_STATE_BUSY; hi2c->i2c_state = I2C_STATE_BUSY;
hi2c->i2c_err = I2C_ERROR_NONE;
/* Disable the selected I2C peripheral */ do {
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE); uint64_t timeout_ref;
/* Reset I2Cx ANOFF bit */ /* Generate Start */
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_ANFOFF); if ((mmio_read_32(hi2c->i2c_base_addr + I2C_OAR1) &
I2C_OAR1_OA1MODE) == 0) {
mmio_write_32(hi2c->i2c_base_addr + I2C_CR2,
(((uint32_t)dev_addr & I2C_CR2_SADD) |
I2C_CR2_START | I2C_CR2_AUTOEND) &
~I2C_CR2_RD_WRN);
} else {
mmio_write_32(hi2c->i2c_base_addr + I2C_CR2,
(((uint32_t)dev_addr & I2C_CR2_SADD) |
I2C_CR2_START | I2C_CR2_ADD10) &
~I2C_CR2_RD_WRN);
}
/* Set analog filter bit*/ /*
mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR1, analog_filter); * No need to Check TC flag, with AUTOEND mode the stop
* is automatically generated.
* Wait until STOPF flag is set or a NACK flag is set.
*/
timeout_ref = timeout_init_us(timeout_ms * 1000);
do {
if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
(I2C_FLAG_STOPF | I2C_FLAG_AF)) != 0U) {
break;
}
/* Enable the selected I2C peripheral */ if (timeout_elapsed(timeout_ref)) {
mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE); notif_i2c_timeout(hi2c);
goto bail;
}
} while (true);
hi2c->i2c_state = I2C_STATE_READY; if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
I2C_FLAG_AF) == 0U) {
if (i2c_wait_flag(hi2c, I2C_FLAG_STOPF, 0,
timeout_ref) != 0) {
goto bail;
}
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR,
I2C_FLAG_STOPF);
hi2c->i2c_state = I2C_STATE_READY;
rc = true;
goto bail;
}
if (i2c_wait_flag(hi2c, I2C_FLAG_STOPF, 0, timeout_ref) != 0) {
goto bail;
}
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_AF);
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
if (i2c_trials == trials) {
mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR2,
I2C_CR2_STOP);
if (i2c_wait_flag(hi2c, I2C_FLAG_STOPF, 0,
timeout_ref) != 0) {
goto bail;
}
mmio_write_32(hi2c->i2c_base_addr + I2C_ICR,
I2C_FLAG_STOPF);
}
i2c_trials++;
} while (i2c_trials < trials);
notif_i2c_timeout(hi2c);
bail:
hi2c->lock = 0; hi2c->lock = 0;
stm32mp_clk_disable(hi2c->clock);
return 0; return rc;
} }
drivers/st/mmc/stm32_sdmmc2.c
View file @ 37cdad2a
...@@ -19,11 +19,7 @@ ...@@ -19,11 +19,7 @@
#include <drivers/mmc.h> #include <drivers/mmc.h>
#include <drivers/st/stm32_gpio.h> #include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32_sdmmc2.h> #include <drivers/st/stm32_sdmmc2.h>
#include <drivers/st/stm32mp1_clk.h> #include <drivers/st/stm32mp_reset.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <drivers/st/stm32mp1_reset.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/utils.h> #include <lib/utils.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
...@@ -123,8 +119,8 @@ ...@@ -123,8 +119,8 @@
SDMMC_STAR_IDMATE | \ SDMMC_STAR_IDMATE | \
SDMMC_STAR_IDMABTC) SDMMC_STAR_IDMABTC)
#define TIMEOUT_10_MS (plat_get_syscnt_freq2() / 100U) #define TIMEOUT_US_10_MS 10000U
#define TIMEOUT_1_S plat_get_syscnt_freq2() #define TIMEOUT_US_1_S 1000000U
#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
...@@ -159,7 +155,7 @@ static void stm32_sdmmc2_init(void) ...@@ -159,7 +155,7 @@ static void stm32_sdmmc2_init(void)
uintptr_t base = sdmmc2_params.reg_base; uintptr_t base = sdmmc2_params.reg_base;
clock_div = div_round_up(sdmmc2_params.clk_rate, clock_div = div_round_up(sdmmc2_params.clk_rate,
STM32MP1_MMC_INIT_FREQ * 2); STM32MP_MMC_INIT_FREQ * 2);
mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
sdmmc2_params.negedge | sdmmc2_params.negedge |
...@@ -185,11 +181,12 @@ static int stm32_sdmmc2_stop_transfer(void) ...@@ -185,11 +181,12 @@ static int stm32_sdmmc2_stop_transfer(void)
static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
{ {
uint64_t timeout;
uint32_t flags_cmd, status; uint32_t flags_cmd, status;
uint32_t flags_data = 0; uint32_t flags_data = 0;
int err = 0; int err = 0;
uintptr_t base = sdmmc2_params.reg_base; uintptr_t base = sdmmc2_params.reg_base;
unsigned int cmd_reg, arg_reg, start; unsigned int cmd_reg, arg_reg;
if (cmd == NULL) { if (cmd == NULL) {
return -EINVAL; return -EINVAL;
...@@ -272,10 +269,10 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) ...@@ -272,10 +269,10 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
status = mmio_read_32(base + SDMMC_STAR); status = mmio_read_32(base + SDMMC_STAR);
start = get_timer(0); timeout = timeout_init_us(TIMEOUT_US_10_MS);
while ((status & flags_cmd) == 0U) { while ((status & flags_cmd) == 0U) {
if (get_timer(start) > TIMEOUT_10_MS) { if (timeout_elapsed(timeout)) {
err = -ETIMEDOUT; err = -ETIMEDOUT;
ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
__func__, cmd->cmd_idx, status); __func__, cmd->cmd_idx, status);
...@@ -339,10 +336,10 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) ...@@ -339,10 +336,10 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
status = mmio_read_32(base + SDMMC_STAR); status = mmio_read_32(base + SDMMC_STAR);
start = get_timer(0); timeout = timeout_init_us(TIMEOUT_US_10_MS);
while ((status & flags_data) == 0U) { while ((status & flags_data) == 0U) {
if (get_timer(start) > TIMEOUT_10_MS) { if (timeout_elapsed(timeout)) {
ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
__func__, cmd->cmd_idx, status); __func__, cmd->cmd_idx, status);
err = -ETIMEDOUT; err = -ETIMEDOUT;
...@@ -364,7 +361,7 @@ err_exit: ...@@ -364,7 +361,7 @@ err_exit:
mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
if (err != 0) { if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) {
int ret_stop = stm32_sdmmc2_stop_transfer(); int ret_stop = stm32_sdmmc2_stop_transfer();
if (ret_stop != 0) { if (ret_stop != 0) {
...@@ -429,15 +426,15 @@ static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) ...@@ -429,15 +426,15 @@ static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width)
if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
if (max_bus_freq >= 52000000U) { if (max_bus_freq >= 52000000U) {
max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ; max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ;
} else { } else {
max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ; max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ;
} }
} else { } else {
if (max_bus_freq >= 50000000U) { if (max_bus_freq >= 50000000U) {
max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ; max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ;
} else { } else {
max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ; max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ;
} }
} }
...@@ -523,7 +520,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) ...@@ -523,7 +520,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
uint32_t *buffer; uint32_t *buffer;
uintptr_t base = sdmmc2_params.reg_base; uintptr_t base = sdmmc2_params.reg_base;
uintptr_t fifo_reg = base + SDMMC_FIFOR; uintptr_t fifo_reg = base + SDMMC_FIFOR;
unsigned int start; uint64_t timeout;
int ret; int ret;
/* Assert buf is 4 bytes aligned */ /* Assert buf is 4 bytes aligned */
...@@ -541,7 +538,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) ...@@ -541,7 +538,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
flags |= SDMMC_STAR_DBCKEND; flags |= SDMMC_STAR_DBCKEND;
} }
start = get_timer(0); timeout = timeout_init_us(TIMEOUT_US_1_S);
do { do {
status = mmio_read_32(base + SDMMC_STAR); status = mmio_read_32(base + SDMMC_STAR);
...@@ -563,7 +560,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) ...@@ -563,7 +560,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
return -EIO; return -EIO;
} }
if (get_timer(start) > TIMEOUT_1_S) { if (timeout_elapsed(timeout)) {
ERROR("%s: timeout 1s (status = %x)\n", ERROR("%s: timeout 1s (status = %x)\n",
__func__, status); __func__, status);
mmio_write_32(base + SDMMC_ICR, mmio_write_32(base + SDMMC_ICR,
...@@ -705,8 +702,6 @@ unsigned long long stm32_sdmmc2_mmc_get_device_size(void) ...@@ -705,8 +702,6 @@ unsigned long long stm32_sdmmc2_mmc_get_device_size(void)
int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
{ {
int ret;
assert((params != NULL) && assert((params != NULL) &&
((params->reg_base & MMC_BLOCK_MASK) == 0U) && ((params->reg_base & MMC_BLOCK_MASK) == 0U) &&
((params->bus_width == MMC_BUS_WIDTH_1) || ((params->bus_width == MMC_BUS_WIDTH_1) ||
...@@ -720,19 +715,14 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) ...@@ -720,19 +715,14 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
return -ENOMEM; return -ENOMEM;
} }
ret = stm32mp1_clk_enable(sdmmc2_params.clock_id); stm32mp_clk_enable(sdmmc2_params.clock_id);
if (ret != 0) {
ERROR("%s: clock %d failed\n", __func__,
sdmmc2_params.clock_id);
return ret;
}
stm32mp1_reset_assert(sdmmc2_params.reset_id); stm32mp_reset_assert(sdmmc2_params.reset_id);
udelay(2); udelay(2);
stm32mp1_reset_deassert(sdmmc2_params.reset_id); stm32mp_reset_deassert(sdmmc2_params.reset_id);
mdelay(1); mdelay(1);
sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id); sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id);
return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,
sdmmc2_params.bus_width, sdmmc2_params.flags, sdmmc2_params.bus_width, sdmmc2_params.flags,
......
drivers/st/pmic/stm32mp_pmic.c
View file @ 37cdad2a
...@@ -5,7 +5,6 @@ ...@@ -5,7 +5,6 @@
*/ */
#include <errno.h> #include <errno.h>
#include <stdbool.h>
#include <libfdt.h> #include <libfdt.h>
...@@ -13,20 +12,12 @@ ...@@ -13,20 +12,12 @@
#include <common/debug.h> #include <common/debug.h>
#include <drivers/delay_timer.h> #include <drivers/delay_timer.h>
#include <drivers/st/stm32_i2c.h>
#include <drivers/st/stm32mp_pmic.h> #include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stpmic1.h> #include <drivers/st/stpmic1.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/utils_def.h> #include <lib/utils_def.h>
/* I2C Timing hard-coded value, for I2C clock source is HSI at 64MHz */
#define I2C_TIMING 0x10D07DB5
#define I2C_TIMEOUT 0xFFFFF
#define MASK_RESET_BUCK3 BIT(2)
#define STPMIC1_LDO12356_OUTPUT_MASK (uint8_t)(GENMASK(6, 2)) #define STPMIC1_LDO12356_OUTPUT_MASK (uint8_t)(GENMASK(6, 2))
#define STPMIC1_LDO12356_OUTPUT_SHIFT 2 #define STPMIC1_LDO12356_OUTPUT_SHIFT 2
#define STPMIC1_LDO3_MODE (uint8_t)(BIT(7)) #define STPMIC1_LDO3_MODE (uint8_t)(BIT(7))
...@@ -46,25 +37,29 @@ static int dt_get_pmic_node(void *fdt) ...@@ -46,25 +37,29 @@ static int dt_get_pmic_node(void *fdt)
return fdt_node_offset_by_compatible(fdt, -1, "st,stpmic1"); return fdt_node_offset_by_compatible(fdt, -1, "st,stpmic1");
} }
bool dt_check_pmic(void) int dt_pmic_status(void)
{ {
int node; int node;
void *fdt; void *fdt;
if (fdt_get_address(&fdt) == 0) { if (fdt_get_address(&fdt) == 0) {
return false; return -ENOENT;
} }
node = dt_get_pmic_node(fdt); node = dt_get_pmic_node(fdt);
if (node < 0) { if (node <= 0) {
VERBOSE("%s: No PMIC node found in DT\n", __func__); return -FDT_ERR_NOTFOUND;
return false;
} }
return fdt_get_status(node); return fdt_get_status(node);
} }
static int dt_pmic_i2c_config(struct dt_node_info *i2c_info) /*
* Get PMIC and its I2C bus configuration from the device tree.
* Return 0 on success, negative on error, 1 if no PMIC node is found.
*/
static int dt_pmic_i2c_config(struct dt_node_info *i2c_info,
struct stm32_i2c_init_s *init)
{ {
int pmic_node, i2c_node; int pmic_node, i2c_node;
void *fdt; void *fdt;
...@@ -76,7 +71,7 @@ static int dt_pmic_i2c_config(struct dt_node_info *i2c_info) ...@@ -76,7 +71,7 @@ static int dt_pmic_i2c_config(struct dt_node_info *i2c_info)
pmic_node = dt_get_pmic_node(fdt); pmic_node = dt_get_pmic_node(fdt);
if (pmic_node < 0) { if (pmic_node < 0) {
return -FDT_ERR_NOTFOUND; return 1;
} }
cuint = fdt_getprop(fdt, pmic_node, "reg", NULL); cuint = fdt_getprop(fdt, pmic_node, "reg", NULL);
...@@ -99,10 +94,10 @@ static int dt_pmic_i2c_config(struct dt_node_info *i2c_info) ...@@ -99,10 +94,10 @@ static int dt_pmic_i2c_config(struct dt_node_info *i2c_info)
return -FDT_ERR_NOTFOUND; return -FDT_ERR_NOTFOUND;
} }
return dt_set_pinctrl_config(i2c_node); return stm32_i2c_get_setup_from_fdt(fdt, i2c_node, init);
} }
int dt_pmic_enable_boot_on_regulators(void) int dt_pmic_configure_boot_on_regulators(void)
{ {
int pmic_node, regulators_node, regulator_node; int pmic_node, regulators_node, regulator_node;
void *fdt; void *fdt;
...@@ -120,14 +115,40 @@ int dt_pmic_enable_boot_on_regulators(void) ...@@ -120,14 +115,40 @@ int dt_pmic_enable_boot_on_regulators(void)
fdt_for_each_subnode(regulator_node, fdt, regulators_node) { fdt_for_each_subnode(regulator_node, fdt, regulators_node) {
const fdt32_t *cuint; const fdt32_t *cuint;
const char *node_name; const char *node_name = fdt_get_name(fdt, regulator_node, NULL);
uint16_t voltage; uint16_t voltage;
int status;
#if defined(IMAGE_BL2)
if ((fdt_getprop(fdt, regulator_node, "regulator-boot-on",
NULL) == NULL) &&
(fdt_getprop(fdt, regulator_node, "regulator-always-on",
NULL) == NULL)) {
#else
if (fdt_getprop(fdt, regulator_node, "regulator-boot-on", if (fdt_getprop(fdt, regulator_node, "regulator-boot-on",
NULL) == NULL) { NULL) == NULL) {
#endif
continue; continue;
} }
if (fdt_getprop(fdt, regulator_node, "regulator-pull-down",
NULL) != NULL) {
status = stpmic1_regulator_pull_down_set(node_name);
if (status != 0) {
return status;
}
}
if (fdt_getprop(fdt, regulator_node, "st,mask-reset",
NULL) != NULL) {
status = stpmic1_regulator_mask_reset_set(node_name);
if (status != 0) {
return status;
}
}
cuint = fdt_getprop(fdt, regulator_node, cuint = fdt_getprop(fdt, regulator_node,
"regulator-min-microvolt", NULL); "regulator-min-microvolt", NULL);
if (cuint == NULL) { if (cuint == NULL) {
...@@ -136,17 +157,13 @@ int dt_pmic_enable_boot_on_regulators(void) ...@@ -136,17 +157,13 @@ int dt_pmic_enable_boot_on_regulators(void)
/* DT uses microvolts, whereas driver awaits millivolts */ /* DT uses microvolts, whereas driver awaits millivolts */
voltage = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U); voltage = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U);
node_name = fdt_get_name(fdt, regulator_node, NULL);
if (stpmic1_is_regulator_enabled(node_name) == 0U) {
int status;
status = stpmic1_regulator_voltage_set(node_name, status = stpmic1_regulator_voltage_set(node_name, voltage);
voltage); if (status != 0) {
if (status != 0) { return status;
return status; }
}
if (stpmic1_is_regulator_enabled(node_name) == 0U) {
status = stpmic1_regulator_enable(node_name); status = stpmic1_regulator_enable(node_name);
if (status != 0) { if (status != 0) {
return status; return status;
...@@ -157,77 +174,77 @@ int dt_pmic_enable_boot_on_regulators(void) ...@@ -157,77 +174,77 @@ int dt_pmic_enable_boot_on_regulators(void)
return 0; return 0;
} }
void initialize_pmic_i2c(void) bool initialize_pmic_i2c(void)
{ {
int ret; int ret;
struct dt_node_info i2c_info; struct dt_node_info i2c_info;
struct i2c_handle_s *i2c = &i2c_handle;
struct stm32_i2c_init_s i2c_init;
if (dt_pmic_i2c_config(&i2c_info) != 0) { ret = dt_pmic_i2c_config(&i2c_info, &i2c_init);
ERROR("I2C configuration failed\n"); if (ret < 0) {
ERROR("I2C configuration failed %d\n", ret);
panic(); panic();
} }
if (stm32mp1_clk_enable((uint32_t)i2c_info.clock) < 0) { if (ret != 0) {
ERROR("I2C clock enable failed\n"); return false;
panic();
} }
/* Initialize PMIC I2C */ /* Initialize PMIC I2C */
i2c_handle.i2c_base_addr = i2c_info.base; i2c->i2c_base_addr = i2c_info.base;
i2c_handle.i2c_init.timing = I2C_TIMING; i2c->dt_status = i2c_info.status;
i2c_handle.i2c_init.own_address1 = pmic_i2c_addr; i2c->clock = i2c_info.clock;
i2c_handle.i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT; i2c_init.own_address1 = pmic_i2c_addr;
i2c_handle.i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE; i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT;
i2c_handle.i2c_init.own_address2 = 0; i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE;
i2c_handle.i2c_init.own_address2_masks = I2C_OAR2_OA2NOMASK; i2c_init.own_address2 = 0;
i2c_handle.i2c_init.general_call_mode = I2C_GENERALCALL_DISABLE; i2c_init.own_address2_masks = I2C_OAR2_OA2NOMASK;
i2c_handle.i2c_init.no_stretch_mode = I2C_NOSTRETCH_DISABLE; i2c_init.general_call_mode = I2C_GENERALCALL_DISABLE;
i2c_init.no_stretch_mode = I2C_NOSTRETCH_DISABLE;
ret = stm32_i2c_init(&i2c_handle); i2c_init.analog_filter = 1;
i2c_init.digital_filter_coef = 0;
ret = stm32_i2c_init(i2c, &i2c_init);
if (ret != 0) { if (ret != 0) {
ERROR("Cannot initialize I2C %x (%d)\n", ERROR("Cannot initialize I2C %x (%d)\n",
i2c_handle.i2c_base_addr, ret); i2c->i2c_base_addr, ret);
panic(); panic();
} }
ret = stm32_i2c_config_analog_filter(&i2c_handle, if (!stm32_i2c_is_device_ready(i2c, pmic_i2c_addr, 1,
I2C_ANALOGFILTER_ENABLE); I2C_TIMEOUT_BUSY_MS)) {
if (ret != 0) { ERROR("I2C device not ready\n");
ERROR("Cannot initialize I2C analog filter (%d)\n", ret);
panic(); panic();
} }
ret = stm32_i2c_is_device_ready(&i2c_handle, (uint16_t)pmic_i2c_addr, 1, stpmic1_bind_i2c(i2c, (uint16_t)pmic_i2c_addr);
I2C_TIMEOUT);
if (ret != 0) {
ERROR("I2C device not ready (%d)\n", ret);
panic();
}
stpmic1_bind_i2c(&i2c_handle, (uint16_t)pmic_i2c_addr); return true;
} }
void initialize_pmic(void) void initialize_pmic(void)
{ {
int status; unsigned long pmic_version;
uint8_t read_val;
initialize_pmic_i2c(); if (!initialize_pmic_i2c()) {
VERBOSE("No PMIC\n");
return;
}
status = stpmic1_register_read(VERSION_STATUS_REG, &read_val); if (stpmic1_get_version(&pmic_version) != 0) {
if (status != 0) { ERROR("Failed to access PMIC\n");
panic(); panic();
} }
INFO("PMIC version = 0x%x\n", read_val); INFO("PMIC version = 0x%02lx\n", pmic_version);
stpmic1_dump_regulators();
/* Keep VDD on during the reset cycle */ #if defined(IMAGE_BL2)
status = stpmic1_register_update(MASK_RESET_BUCK_REG, if (dt_pmic_configure_boot_on_regulators() != 0) {
MASK_RESET_BUCK3,
MASK_RESET_BUCK3);
if (status != 0) {
panic(); panic();
} };
#endif
} }
int pmic_ddr_power_init(enum ddr_type ddr_type) int pmic_ddr_power_init(enum ddr_type ddr_type)
......
drivers/st/pmic/stpmic1.c
View file @ 37cdad2a
...@@ -8,7 +8,8 @@ ...@@ -8,7 +8,8 @@
#include <common/debug.h> #include <common/debug.h>
#include <drivers/st/stpmic1.h> #include <drivers/st/stpmic1.h>
#include <plat/common/platform.h>
#define I2C_TIMEOUT_MS 25
struct regul_struct { struct regul_struct {
const char *dt_node_name; const char *dt_node_name;
...@@ -677,8 +678,9 @@ int stpmic1_regulator_voltage_get(const char *name) ...@@ -677,8 +678,9 @@ int stpmic1_regulator_voltage_get(const char *name)
int stpmic1_register_read(uint8_t register_id, uint8_t *value) int stpmic1_register_read(uint8_t register_id, uint8_t *value)
{ {
return stm32_i2c_mem_read(pmic_i2c_handle, pmic_i2c_addr, return stm32_i2c_mem_read(pmic_i2c_handle, pmic_i2c_addr,
(uint16_t)register_id, I2C_MEMADD_SIZE_8BIT, (uint16_t)register_id,
value, 1, 100000); I2C_MEMADD_SIZE_8BIT, value,
1, I2C_TIMEOUT_MS);
} }
int stpmic1_register_write(uint8_t register_id, uint8_t value) int stpmic1_register_write(uint8_t register_id, uint8_t value)
...@@ -687,7 +689,8 @@ int stpmic1_register_write(uint8_t register_id, uint8_t value) ...@@ -687,7 +689,8 @@ int stpmic1_register_write(uint8_t register_id, uint8_t value)
status = stm32_i2c_mem_write(pmic_i2c_handle, pmic_i2c_addr, status = stm32_i2c_mem_write(pmic_i2c_handle, pmic_i2c_addr,
(uint16_t)register_id, (uint16_t)register_id,
I2C_MEMADD_SIZE_8BIT, &value, 1, 100000); I2C_MEMADD_SIZE_8BIT, &value,
1, I2C_TIMEOUT_MS);
#if ENABLE_ASSERTIONS #if ENABLE_ASSERTIONS
if (status != 0) { if (status != 0) {
......
drivers/st/reset/stm32mp1_reset.c
View file @ 37cdad2a
/* /*
* Copyright (c) 2018, STMicroelectronics - All Rights Reserved * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -10,32 +10,53 @@ ...@@ -10,32 +10,53 @@
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h> #include <common/debug.h>
#include <drivers/st/stm32mp1_rcc.h> #include <drivers/delay_timer.h>
#include <drivers/st/stm32mp1_reset.h> #include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/utils_def.h> #include <lib/utils_def.h>
#define RST_CLR_OFFSET 4U #define RESET_TIMEOUT_US_1MS U(1000)
void stm32mp1_reset_assert(uint32_t id) static uint32_t id2reg_offset(unsigned int reset_id)
{ {
uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t); return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t);
uint32_t bit = id % (uint32_t)__LONG_BIT; }
mmio_write_32(RCC_BASE + offset, BIT(bit)); static uint8_t id2reg_bit_pos(unsigned int reset_id)
while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) == 0U) { {
; return (uint8_t)(reset_id & GENMASK(4, 0));
}
} }
void stm32mp1_reset_deassert(uint32_t id) void stm32mp_reset_assert(uint32_t id)
{ {
uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) + uint32_t offset = id2reg_offset(id);
RST_CLR_OFFSET; uint32_t bitmsk = BIT(id2reg_bit_pos(id));
uint32_t bit = id % (uint32_t)__LONG_BIT; uint64_t timeout_ref;
uintptr_t rcc_base = stm32mp_rcc_base();
mmio_write_32(rcc_base + offset, bitmsk);
timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
while ((mmio_read_32(rcc_base + offset) & bitmsk) == 0U) {
if (timeout_elapsed(timeout_ref)) {
panic();
}
}
}
mmio_write_32(RCC_BASE + offset, BIT(bit)); void stm32mp_reset_deassert(uint32_t id)
while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) != 0U) { {
; uint32_t offset = id2reg_offset(id) + RCC_RSTCLRR_OFFSET;
uint32_t bitmsk = BIT(id2reg_bit_pos(id));
uint64_t timeout_ref;
uintptr_t rcc_base = stm32mp_rcc_base();
mmio_write_32(rcc_base + offset, bitmsk);
timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
while ((mmio_read_32(rcc_base + offset) & bitmsk) != 0U) {
if (timeout_elapsed(timeout_ref)) {
panic();
}
} }
} }
fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi 0 → 100644
View file @ 37cdad2a
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
/* STM32MP157C DK1/DK2 BOARD configuration
* 1x DDR3L 4Gb, 16-bit, 533MHz.
* Reference used NT5CC256M16DP-DI from NANYA
*
* DDR type / Platform DDR3/3L
* freq 533MHz
* width 16
* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
* DDR density 4
* timing mode optimized
* Scheduling/QoS options : type = 2
* address mapping : RBC
* Tc > + 85C : N
*/
#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.41"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
#define DDR_MSTR 0x00041401
#define DDR_MRCTRL0 0x00000010
#define DDR_MRCTRL1 0x00000000
#define DDR_DERATEEN 0x00000000
#define DDR_DERATEINT 0x00800000
#define DDR_PWRCTL 0x00000000
#define DDR_PWRTMG 0x00400010
#define DDR_HWLPCTL 0x00000000
#define DDR_RFSHCTL0 0x00210000
#define DDR_RFSHCTL3 0x00000000
#define DDR_RFSHTMG 0x0081008B
#define DDR_CRCPARCTL0 0x00000000
#define DDR_DRAMTMG0 0x121B2414
#define DDR_DRAMTMG1 0x000A041C
#define DDR_DRAMTMG2 0x0608090F
#define DDR_DRAMTMG3 0x0050400C
#define DDR_DRAMTMG4 0x08040608
#define DDR_DRAMTMG5 0x06060403
#define DDR_DRAMTMG6 0x02020002
#define DDR_DRAMTMG7 0x00000202
#define DDR_DRAMTMG8 0x00001005
#define DDR_DRAMTMG14 0x000000A0
#define DDR_ZQCTL0 0xC2000040
#define DDR_DFITMG0 0x02060105
#define DDR_DFITMG1 0x00000202
#define DDR_DFILPCFG0 0x07000000
#define DDR_DFIUPD0 0xC0400003
#define DDR_DFIUPD1 0x00000000
#define DDR_DFIUPD2 0x00000000
#define DDR_DFIPHYMSTR 0x00000000
#define DDR_ADDRMAP1 0x00070707
#define DDR_ADDRMAP2 0x00000000
#define DDR_ADDRMAP3 0x1F000000
#define DDR_ADDRMAP4 0x00001F1F
#define DDR_ADDRMAP5 0x06060606
#define DDR_ADDRMAP6 0x0F060606
#define DDR_ADDRMAP9 0x00000000
#define DDR_ADDRMAP10 0x00000000
#define DDR_ADDRMAP11 0x00000000
#define DDR_ODTCFG 0x06000600
#define DDR_ODTMAP 0x00000001
#define DDR_SCHED 0x00000C01
#define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x01000001
#define DDR_PERFLPR1 0x08000200
#define DDR_PERFWR1 0x08000400
#define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000
#define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000010
#define DDR_PCFGR_0 0x00010000
#define DDR_PCFGW_0 0x00000000
#define DDR_PCFGQOS0_0 0x02100C03
#define DDR_PCFGQOS1_0 0x00800100
#define DDR_PCFGWQOS0_0 0x01100C03
#define DDR_PCFGWQOS1_0 0x01000200
#define DDR_PCFGR_1 0x00010000
#define DDR_PCFGW_1 0x00000000
#define DDR_PCFGQOS0_1 0x02100C03
#define DDR_PCFGQOS1_1 0x00800040
#define DDR_PCFGWQOS0_1 0x01100C03
#define DDR_PCFGWQOS1_1 0x01000200
#define DDR_PGCR 0x01442E02
#define DDR_PTR0 0x0022AA5B
#define DDR_PTR1 0x04841104
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200001F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
#define DDR_DTPR2 0x10023600
#define DDR_MR0 0x00000840
#define DDR_MR1 0x00000000
#define DDR_MR2 0x00000208
#define DDR_MR3 0x00000000
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
fdts/stm32mp157a-dk1.dts 0 → 100644
View file @ 37cdad2a
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2018-2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>.
*/
/dts-v1/;
#include "stm32mp157c.dtsi"
#include "stm32mp157cac-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
aliases {
serial0 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&clk_hse {
st,digbypass;
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
st,main-control-register = <0x04>;
st,vin-control-register = <0xc0>;
st,usb-control-register = <0x20>;
regulators {
compatible = "st,stpmic1-regulators";
ldo1-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo6-supply = <&v3v3>;
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd_ddr: buck2 {
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
v3v3: buck4 {
regulator-name = "v3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
regulator-initial-mode = <0>;
};
v1v8_audio: ldo1 {
regulator-name = "v1v8_audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
v3v3_hdmi: ldo2 {
regulator-name = "v3v3_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdda: ldo5 {
regulator-name = "vdda";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-boot-on;
};
v1v2_hdmi: ldo6 {
regulator-name = "v1v2_hdmi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
regulator-over-current-protection;
};
};
};
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&rng1 {
status = "okay";
};
&rtc {
status = "okay";
};
&sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
broken-cd;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
status = "okay";
};
/* ATF Specific */
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
/ {
aliases {
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio25 = &gpioz;
i2c3 = &i2c4;
};
soc {
stgen: stgen@5C008000 {
compatible = "st,stm32-stgen";
reg = <0x5C008000 0x1000>;
status = "okay";
};
};
};
/* CLOCK init */
&rcc {
secure-status = "disabled";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4Q
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
};
};
fdts/stm32mp157c-dk2.dts 0 → 100644
View file @ 37cdad2a
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>.
*/
/dts-v1/;
#include "stm32mp157a-dk1.dts"
/ {
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
};
fdts/stm32mp157c-ed1.dts
View file @ 37cdad2a
...@@ -55,7 +55,7 @@ ...@@ -55,7 +55,7 @@
vddcore: buck1 { vddcore: buck1 {
regulator-name = "vddcore"; regulator-name = "vddcore";
regulator-min-microvolt = <800000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-always-on; regulator-always-on;
regulator-initial-mode = <0>; regulator-initial-mode = <0>;
......
fdts/stm32mp157cac-pinctrl.dtsi 0 → 100644
View file @ 37cdad2a
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
*/
#include "stm32mp157-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller@50002000 {
st,package = <STM32MP157CAC>;
gpioa: gpio@50002000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@50003000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@50004000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@50005000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@50006000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@50007000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@50008000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@50009000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@5000a000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 0 128 12>;
};
};
pinctrl_z: pin-controller-z@54004000 {
st,package = <STM32MP157CAC>;
gpioz: gpio@54004000 {
status = "okay";
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
};
};
};
};
include/drivers/st/stm32_i2c.h
View file @ 37cdad2a
/* /*
* Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -111,94 +111,113 @@ ...@@ -111,94 +111,113 @@
#define I2C_ICR_TIMOUTCF BIT(12) #define I2C_ICR_TIMOUTCF BIT(12)
#define I2C_ICR_ALERTCF BIT(13) #define I2C_ICR_ALERTCF BIT(13)
struct stm32_i2c_init_s { enum i2c_speed_e {
uint32_t timing; /* Specifies the I2C_TIMINGR_register value I2C_SPEED_STANDARD, /* 100 kHz */
* This parameter is calculated by referring I2C_SPEED_FAST, /* 400 kHz */
* to I2C initialization section in Reference I2C_SPEED_FAST_PLUS, /* 1 MHz */
* manual. };
*/
#define STANDARD_RATE 100000
uint32_t own_address1; /* Specifies the first device own address. #define FAST_RATE 400000
* This parameter can be a 7-bit or 10-bit #define FAST_PLUS_RATE 1000000
* address.
*/
uint32_t addressing_mode; /* Specifies if 7-bit or 10-bit addressing
* mode is selected.
* This parameter can be a value of @ref
* I2C_ADDRESSING_MODE.
*/
uint32_t dual_address_mode; /* Specifies if dual addressing mode is
* selected.
* This parameter can be a value of @ref
* I2C_DUAL_ADDRESSING_MODE.
*/
uint32_t own_address2; /* Specifies the second device own address
* if dual addressing mode is selected.
* This parameter can be a 7-bit address.
*/
uint32_t own_address2_masks; /* Specifies the acknowledge mask address
* second device own address if dual
* addressing mode is selected.
* This parameter can be a value of @ref
* I2C_OWN_ADDRESS2_MASKS.
*/
uint32_t general_call_mode; /* Specifies if general call mode is
* selected.
* This parameter can be a value of @ref
* I2C_GENERAL_CALL_ADDRESSING_MODE.
*/
uint32_t no_stretch_mode; /* Specifies if nostretch mode is
* selected.
* This parameter can be a value of @ref
* I2C_NOSTRETCH_MODE.
*/
struct stm32_i2c_init_s {
uint32_t own_address1; /*
* Specifies the first device own
* address. This parameter can be a
* 7-bit or 10-bit address.
*/
uint32_t addressing_mode; /*
* Specifies if 7-bit or 10-bit
* addressing mode is selected.
* This parameter can be a value of
* @ref I2C_ADDRESSING_MODE.
*/
uint32_t dual_address_mode; /*
* Specifies if dual addressing mode is
* selected.
* This parameter can be a value of @ref
* I2C_DUAL_ADDRESSING_MODE.
*/
uint32_t own_address2; /*
* Specifies the second device own
* address if dual addressing mode is
* selected. This parameter can be a
* 7-bit address.
*/
uint32_t own_address2_masks; /*
* Specifies the acknowledge mask
* address second device own address
* if dual addressing mode is selected
* This parameter can be a value of @ref
* I2C_OWN_ADDRESS2_MASKS.
*/
uint32_t general_call_mode; /*
* Specifies if general call mode is
* selected.
* This parameter can be a value of @ref
* I2C_GENERAL_CALL_ADDRESSING_MODE.
*/
uint32_t no_stretch_mode; /*
* Specifies if nostretch mode is
* selected.
* This parameter can be a value of @ref
* I2C_NOSTRETCH_MODE.
*/
uint32_t rise_time; /*
* Specifies the SCL clock pin rising
* time in nanoseconds.
*/
uint32_t fall_time; /*
* Specifies the SCL clock pin falling
* time in nanoseconds.
*/
enum i2c_speed_e speed_mode; /*
* Specifies the I2C clock source
* frequency mode.
* This parameter can be a value of @ref
* i2c_speed_mode_e.
*/
int analog_filter; /*
* Specifies if the I2C analog noise
* filter is selected.
* This parameter can be 0 (filter
* off), all other values mean filter
* on.
*/
uint8_t digital_filter_coef; /*
* Specifies the I2C digital noise
* filter coefficient.
* This parameter can be a value
* between 0 and
* STM32_I2C_DIGITAL_FILTER_MAX.
*/
}; };
enum i2c_state_e { enum i2c_state_e {
I2C_STATE_RESET = 0x00U, /* Peripheral is not yet I2C_STATE_RESET = 0x00U, /* Not yet initialized */
* initialized. I2C_STATE_READY = 0x20U, /* Ready for use */
*/ I2C_STATE_BUSY = 0x24U, /* Internal process ongoing */
I2C_STATE_READY = 0x20U, /* Peripheral Initialized I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission ongoing */
* and ready for use. I2C_STATE_BUSY_RX = 0x22U, /* Data Reception ongoing */
*/
I2C_STATE_BUSY = 0x24U, /* An internal process is
* ongoing.
*/
I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission process
* is ongoing.
*/
I2C_STATE_BUSY_RX = 0x22U, /* Data Reception process
* is ongoing.
*/
I2C_STATE_LISTEN = 0x28U, /* Address Listen Mode is
* ongoing.
*/
I2C_STATE_BUSY_TX_LISTEN = 0x29U, /* Address Listen Mode
* and Data Transmission
* process is ongoing.
*/
I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /* Address Listen Mode
* and Data Reception
* process is ongoing.
*/
I2C_STATE_ABORT = 0x60U, /* Abort user request ongoing. */
I2C_STATE_TIMEOUT = 0xA0U, /* Timeout state. */
I2C_STATE_ERROR = 0xE0U /* Error. */
}; };
enum i2c_mode_e { enum i2c_mode_e {
I2C_MODE_NONE = 0x00U, /* No I2C communication on going. */ I2C_MODE_NONE = 0x00U, /* No active communication */
I2C_MODE_MASTER = 0x10U, /* I2C communication is in Master Mode. */ I2C_MODE_MASTER = 0x10U, /* Communication in Master Mode */
I2C_MODE_SLAVE = 0x20U, /* I2C communication is in Slave Mode. */ I2C_MODE_SLAVE = 0x20U, /* Communication in Slave Mode */
I2C_MODE_MEM = 0x40U /* I2C communication is in Memory Mode. */ I2C_MODE_MEM = 0x40U /* Communication in Memory Mode */
}; };
...@@ -213,26 +232,12 @@ enum i2c_mode_e { ...@@ -213,26 +232,12 @@ enum i2c_mode_e {
struct i2c_handle_s { struct i2c_handle_s {
uint32_t i2c_base_addr; /* Registers base address */ uint32_t i2c_base_addr; /* Registers base address */
unsigned int dt_status; /* DT nsec/sec status */
struct stm32_i2c_init_s i2c_init; /* Communication parameters */ unsigned int clock; /* Clock reference */
uint8_t lock; /* Locking object */
uint8_t *p_buff; /* Pointer to transfer buffer */ enum i2c_state_e i2c_state; /* Communication state */
enum i2c_mode_e i2c_mode; /* Communication mode */
uint16_t xfer_size; /* Transfer size */ uint32_t i2c_err; /* Error code */
uint16_t xfer_count; /* Transfer counter */
uint32_t prev_state; /* Communication previous
* state
*/
uint8_t lock; /* Locking object */
enum i2c_state_e i2c_state; /* Communication state */
enum i2c_mode_e i2c_mode; /* Communication mode */
uint32_t i2c_err; /* Error code */
}; };
#define I2C_ADDRESSINGMODE_7BIT 0x00000001U #define I2C_ADDRESSINGMODE_7BIT 0x00000001U
...@@ -250,15 +255,15 @@ struct i2c_handle_s { ...@@ -250,15 +255,15 @@ struct i2c_handle_s {
#define I2C_MEMADD_SIZE_8BIT 0x00000001U #define I2C_MEMADD_SIZE_8BIT 0x00000001U
#define I2C_MEMADD_SIZE_16BIT 0x00000002U #define I2C_MEMADD_SIZE_16BIT 0x00000002U
#define I2C_RELOAD_MODE I2C_CR2_RELOAD #define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE 0x00000000U #define I2C_SOFTEND_MODE 0x00000000U
#define I2C_NO_STARTSTOP 0x00000000U #define I2C_NO_STARTSTOP 0x00000000U
#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
I2C_CR2_RD_WRN) I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
#define I2C_FLAG_TXE I2C_ISR_TXE #define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS #define I2C_FLAG_TXIS I2C_ISR_TXIS
...@@ -281,21 +286,36 @@ struct i2c_handle_s { ...@@ -281,21 +286,36 @@ struct i2c_handle_s {
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN) I2C_CR2_RD_WRN)
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) #define I2C_TIMEOUT_BUSY_MS 25U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
int stm32_i2c_init(struct i2c_handle_s *hi2c); #define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/* STM32 specific defines */
#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
#define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD
#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
#define STM32_I2C_DIGITAL_FILTER_MAX 16
int stm32_i2c_get_setup_from_fdt(void *fdt, int node,
struct stm32_i2c_init_s *init);
int stm32_i2c_init(struct i2c_handle_s *hi2c,
struct stm32_i2c_init_s *init_data);
int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr, int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size, uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout); uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr, int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size, uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout); uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr, int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t trials, uint32_t timeout); uint8_t *p_data, uint16_t size,
uint32_t timeout_ms);
int stm32_i2c_config_analog_filter(struct i2c_handle_s *hi2c, int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t analog_filter); uint8_t *p_data, uint16_t size,
uint32_t timeout_ms);
bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t trials, uint32_t timeout_ms);
#endif /* STM32_I2C_H */ #endif /* STM32_I2C_H */
include/drivers/st/stm32mp1_clk.h
View file @ 37cdad2a
/* /*
* Copyright (c) 2018, STMicroelectronics - All Rights Reserved * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -7,25 +7,42 @@ ...@@ -7,25 +7,42 @@
#ifndef STM32MP1_CLK_H #ifndef STM32MP1_CLK_H
#define STM32MP1_CLK_H #define STM32MP1_CLK_H
#include <stdbool.h>
#include <arch_helpers.h> #include <arch_helpers.h>
int stm32mp1_clk_probe(void); int stm32mp1_clk_probe(void);
int stm32mp1_clk_init(void); int stm32mp1_clk_init(void);
bool stm32mp1_clk_is_enabled(unsigned long id);
int stm32mp1_clk_enable(unsigned long id);
int stm32mp1_clk_disable(unsigned long id);
unsigned long stm32mp1_clk_get_rate(unsigned long id);
void stm32mp1_stgen_increment(unsigned long long offset_in_ms);
static inline uint32_t get_timer(uint32_t base) bool stm32mp1_rcc_is_secure(void);
void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure);
void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure);
static inline void stm32mp1_clk_enable_non_secure(unsigned long id)
{
__stm32mp1_clk_enable(id, false);
}
static inline void stm32mp1_clk_enable_secure(unsigned long id)
{
__stm32mp1_clk_enable(id, true);
}
static inline void stm32mp1_clk_disable_non_secure(unsigned long id)
{ {
if (base == 0U) { __stm32mp1_clk_disable(id, false);
return (uint32_t)(~read_cntpct_el0()); }
}
return base - (uint32_t)(~read_cntpct_el0()); static inline void stm32mp1_clk_disable_secure(unsigned long id)
{
__stm32mp1_clk_disable(id, true);
} }
unsigned int stm32mp1_clk_get_refcount(unsigned long id);
/* SMP protection on RCC registers access */
void stm32mp1_clk_rcc_regs_lock(void);
void stm32mp1_clk_rcc_regs_unlock(void);
void stm32mp1_stgen_increment(unsigned long long offset_in_ms);
#endif /* STM32MP1_CLK_H */ #endif /* STM32MP1_CLK_H */
include/drivers/st/stm32mp1_clkfunc.h
View file @ 37cdad2a
/* /*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -18,7 +18,6 @@ enum stm32mp_osc_id { ...@@ -18,7 +18,6 @@ enum stm32mp_osc_id {
_LSI, _LSI,
_LSE, _LSE,
_I2S_CKIN, _I2S_CKIN,
_USB_PHY_48,
NB_OSC, NB_OSC,
_UNKNOWN_OSC_ID = 0xFF _UNKNOWN_OSC_ID = 0xFF
}; };
...@@ -31,14 +30,4 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, ...@@ -31,14 +30,4 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
const char *prop_name, const char *prop_name,
uint32_t dflt_value); uint32_t dflt_value);
uint32_t fdt_rcc_read_addr(void);
int fdt_rcc_read_uint32_array(const char *prop_name,
uint32_t *array, uint32_t count);
int fdt_rcc_subnode_offset(const char *name);
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
bool fdt_get_rcc_secure_status(void);
uintptr_t fdt_get_stgen_base(void);
int fdt_get_clock_id(int node);
#endif /* STM32MP1_CLKFUNC_H */ #endif /* STM32MP1_CLKFUNC_H */
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