Commit 3d36d8e6 authored by Samuel Holland's avatar Samuel Holland
Browse files

allwinner: Fix non-default PRELOADED_BL33_BASE



While the Allwinner platform code nominally supported a custom
PRELOADED_BL33_BASE, some references to the BL33 load address used
another constant: PLAT_SUNXI_NS_IMAGE_OFFSET. To allow the DTB search
code to work if a U-Boot BL33 is loaded to a custom address,
consistently use PRELOADED_BL33_BASE. And to avoid this confusion in
the future, remove the other constant.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Change-Id: Ie6b97ae1fdec95d784676aef39200bef161471b0
parent 852e4940
...@@ -49,6 +49,9 @@ ERRATA_A53_835769 := 1 ...@@ -49,6 +49,9 @@ ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1 ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1 ERRATA_A53_855873 := 1
# The traditional U-Boot load address is 160MB into DRAM.
PRELOADED_BL33_BASE ?= 0x4a000000
# The reset vector can be changed for each CPU. # The reset vector can be changed for each CPU.
PROGRAMMABLE_RESET_ADDRESS := 1 PROGRAMMABLE_RESET_ADDRESS := 1
......
...@@ -25,9 +25,6 @@ ...@@ -25,9 +25,6 @@
#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
/* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */
#define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20))
/* How much memory to reserve as secure for BL32, if configured */ /* How much memory to reserve as secure for BL32, if configured */
#define SUNXI_DRAM_SEC_SIZE (32U << 20) #define SUNXI_DRAM_SEC_SIZE (32U << 20)
......
...@@ -57,7 +57,7 @@ static void *sunxi_find_dtb(void) ...@@ -57,7 +57,7 @@ static void *sunxi_find_dtb(void)
for (i = 0; i < 2048 / sizeof(uint64_t); i++) { for (i = 0; i < 2048 / sizeof(uint64_t); i++) {
uint32_t *dtb_base; uint32_t *dtb_base;
if (u_boot_base[i] != PLAT_SUNXI_NS_IMAGE_OFFSET) if (u_boot_base[i] != PRELOADED_BL33_BASE)
continue; continue;
/* Does the suspected U-Boot size look anyhow reasonable? */ /* Does the suspected U-Boot size look anyhow reasonable? */
...@@ -96,7 +96,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, ...@@ -96,7 +96,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
* Tell BL31 where the non-trusted software image * Tell BL31 where the non-trusted software image
* is located and the entry state information * is located and the entry state information
*/ */
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS); DISABLE_ALL_EXCEPTIONS);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
......
...@@ -27,7 +27,7 @@ static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { ...@@ -27,7 +27,7 @@ static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
MT_RW_DATA | MT_SECURE), MT_RW_DATA | MT_SECURE),
MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, MAP_REGION(PRELOADED_BL33_BASE,
SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE,
SUNXI_DRAM_MAP_SIZE, SUNXI_DRAM_MAP_SIZE,
MT_RO_DATA | MT_NS), MT_RO_DATA | MT_NS),
...@@ -39,15 +39,6 @@ unsigned int plat_get_syscnt_freq2(void) ...@@ -39,15 +39,6 @@ unsigned int plat_get_syscnt_freq2(void)
return SUNXI_OSC24M_CLK_IN_HZ; return SUNXI_OSC24M_CLK_IN_HZ;
} }
uintptr_t plat_get_ns_image_entrypoint(void)
{
#ifdef PRELOADED_BL33_BASE
return PRELOADED_BL33_BASE;
#else
return PLAT_SUNXI_NS_IMAGE_OFFSET;
#endif
}
void sunxi_configure_mmu_el3(int flags) void sunxi_configure_mmu_el3(int flags)
{ {
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
......
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