Merge changes from topic "renesas-bsp203" into integration

* changes:
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3
  rcar_gen3: drivers: Change to restore timer counter value at resume
  rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2
  rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
  rcar_gen3: drivers: qos: change subslot cycle
  rcar_gen3: drivers: board: Add new board revision for H3ULCB
  rcar_gen3: plat: Change periodic write DQ training option.

plat/renesas/rcar/plat_pm.c

 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -35,8 +35,6 @@
 #define CLUSTER_PWR_STATE(s)	((s)->pwr_domain_state[MPIDR_AFFLVL1])
 #define CORE_PWR_STATE(s)	((s)->pwr_domain_state[MPIDR_AFFLVL0])
 
-uint64_t rcar_stack_generic_timer[5] __attribute__ ((section("data")));
-
 extern void rcar_pwrc_restore_generic_timer(uint64_t *stack);
 extern void plat_rcar_gic_driver_init(void);
 extern void plat_rcar_gic_init(void);
@@ -150,11 +148,7 @@ static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
 	if (cluster_type == RCAR_CLUSTER_A53A57)
 		plat_cci_init();
 
-	rcar_pwrc_restore_generic_timer(rcar_stack_generic_timer);
-
-	/* start generic timer */
-	write_cntfrq_el0(plat_get_syscnt_freq2());
-	mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
+	rcar_pwrc_restore_timer_state();
 	rcar_pwrc_setup();
 	rcar_pwrc_code_copy_to_system_ram();
 

plat/renesas/rcar/platform.mk

@@ -265,7 +265,7 @@ $(eval $(call add_define,RCAR_REF_INT))
 
 # Process RCAR_REWT_TRAINING flag
 ifndef RCAR_REWT_TRAINING
-RCAR_REWT_TRAINING := 0
+RCAR_REWT_TRAINING := 1
 endif
 $(eval $(call add_define,RCAR_REWT_TRAINING))