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Commit 4b9d01d5 authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by TrustedFirmware Code Review
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Merge changes from topic "renesas-bsp203" into integration 

* changes:
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3
  rcar_gen3: drivers: Change to restore timer counter value at resume
  rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2
  rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
  rcar_gen3: drivers: qos: change subslot cycle
  rcar_gen3: drivers: board: Add new board revision for H3ULCB
  rcar_gen3: plat: Change periodic write DQ training option.
parents 2d212479 b028f2c5
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drivers/renesas/rcar/board/board.c
View file @ 4b9d01d5
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define SXS_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define SXS_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define SX_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define SX_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define SKP_ID { 0x10U, 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define SKP_ID { 0x10U, 0x10U, 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define SK_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define SK_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
......
drivers/renesas/rcar/console/rcar_printf.c
View file @ 4b9d01d5
/* /*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -94,9 +94,6 @@ int32_t rcar_log_init(void) ...@@ -94,9 +94,6 @@ int32_t rcar_log_init(void)
sizeof(t_log->header.head)); sizeof(t_log->header.head));
t_log->header.index = 0U; t_log->header.index = 0U;
t_log->header.size = 0U; t_log->header.size = 0U;
#ifndef IMAGE_BL2
rcar_stack_generic_timer[INDEX_TIMER_COUNT] = 0U;
#endif
} }
rcar_lock_init(); rcar_lock_init();
......
drivers/renesas/rcar/console/rcar_printf.h
View file @ 4b9d01d5
/* /*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -12,8 +12,4 @@ ...@@ -12,8 +12,4 @@
int32_t rcar_set_log_data(int32_t c); int32_t rcar_set_log_data(int32_t c);
int32_t rcar_log_init(void); int32_t rcar_log_init(void);
#if IMAGE_BL31
extern uint64_t rcar_stack_generic_timer[5];
#endif
#endif /* RCAR_PRINTF_H */ #endif /* RCAR_PRINTF_H */
drivers/renesas/rcar/pwrc/call_sram.S
View file @ 4b9d01d5
/* /*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include "rcar_def.h"
.global rcar_pwrc_switch_stack .global rcar_pwrc_switch_stack
.global rcar_pwrc_save_generic_timer
.global rcar_pwrc_restore_generic_timer
#define OFFSET_SP_X9_X10 (0x00)
#define OFFSET_CNTFID0 (0x10)
#define OFFSET_CNTPCT_EL0 (0x18)
#define OFFSET_TIMER_COUNT (0x20)
/* /*
* x0 : jump address, * x0 : jump address,
...@@ -54,37 +46,3 @@ func rcar_pwrc_switch_stack ...@@ -54,37 +46,3 @@ func rcar_pwrc_switch_stack
ldp x29, x30, [sp,#-16] ldp x29, x30, [sp,#-16]
ret ret
endfunc rcar_pwrc_switch_stack endfunc rcar_pwrc_switch_stack
/* x0 : stack pointer base address */
func rcar_pwrc_save_generic_timer
stp x9, x10, [x0, #OFFSET_SP_X9_X10]
/* save CNTFID0 and cntpct_el0 */
mov_imm x10, (RCAR_CNTC_BASE + CNTFID_OFF)
ldr x9, [x10]
mrs x10, cntpct_el0
stp x9, x10, [x0, #OFFSET_CNTFID0]
ldp x9, x10, [x0, #OFFSET_SP_X9_X10]
ret
endfunc rcar_pwrc_save_generic_timer
/* x0 : Stack pointer base address */
func rcar_pwrc_restore_generic_timer
stp x9, x10, [x0, #OFFSET_SP_X9_X10]
/* restore CNTFID0 and cntpct_el0 */
ldr x10, [x0, #OFFSET_CNTFID0]
mov_imm x9, (RCAR_CNTC_BASE + CNTFID_OFF)
str x10, [x9]
ldp x9, x10, [x0, #OFFSET_CNTPCT_EL0]
add x9, x9, x10
str x9, [x0, #OFFSET_TIMER_COUNT]
ldp x9, x10, [x0, #OFFSET_SP_X9_X10]
ret
endfunc rcar_pwrc_restore_generic_timer
drivers/renesas/rcar/pwrc/pwrc.c
View file @ 4b9d01d5
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include <lib/bakery_lock.h> #include <lib/bakery_lock.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h> #include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include "iic_dvfs.h" #include "iic_dvfs.h"
#include "rcar_def.h" #include "rcar_def.h"
...@@ -50,6 +51,7 @@ RCAR_INSTANTIATE_LOCK ...@@ -50,6 +51,7 @@ RCAR_INSTANTIATE_LOCK
#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U) #define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U) #define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
#define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U) #define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
#define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
#define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U) #define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
#define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U) #define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
#define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U) #define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
...@@ -61,6 +63,7 @@ RCAR_INSTANTIATE_LOCK ...@@ -61,6 +63,7 @@ RCAR_INSTANTIATE_LOCK
#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0)) #define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0)) #define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
#define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U) #define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
#define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U) #define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U) #define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U) #define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
...@@ -124,6 +127,14 @@ RCAR_INSTANTIATE_LOCK ...@@ -124,6 +127,14 @@ RCAR_INSTANTIATE_LOCK
#define RST_MODEMR (RST_BASE + 0x0060U) #define RST_MODEMR (RST_BASE + 0x0060U)
#define RST_MODEMR_BIT0 (0x00000001U) #define RST_MODEMR_BIT0 (0x00000001U)
#define RCAR_CNTCR_OFF (0x00U)
#define RCAR_CNTCVL_OFF (0x08U)
#define RCAR_CNTCVU_OFF (0x0CU)
#define RCAR_CNTFID_OFF (0x20U)
#define RCAR_CNTCR_EN ((uint32_t)1U << 0U)
#define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U)
#if PMIC_ROHM_BD9571 #if PMIC_ROHM_BD9571
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4)) #define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
#define PMIC_BKUP_MODE_CNT (0x20U) #define PMIC_BKUP_MODE_CNT (0x20U)
...@@ -321,6 +332,39 @@ done: ...@@ -321,6 +332,39 @@ done:
rcar_lock_release(); rcar_lock_release();
} }
static uint64_t rcar_pwrc_saved_cntpct_el0;
static uint32_t rcar_pwrc_saved_cntfid;
#if RCAR_SYSTEM_SUSPEND
static void rcar_pwrc_save_timer_state(void)
{
rcar_pwrc_saved_cntpct_el0 = read_cntpct_el0();
rcar_pwrc_saved_cntfid =
mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
}
#endif
void rcar_pwrc_restore_timer_state(void)
{
/* Stop timer before restoring counter value */
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 0U);
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVL_OFF),
(uint32_t)(rcar_pwrc_saved_cntpct_el0 & 0xFFFFFFFFU));
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVU_OFF),
(uint32_t)(rcar_pwrc_saved_cntpct_el0 >> 32U));
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF),
rcar_pwrc_saved_cntfid);
/* Start generic timer back */
write_cntfrq_el0((u_register_t)plat_get_syscnt_freq2());
mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF),
(RCAR_CNTCR_FCREQ(0U) | RCAR_CNTCR_EN));
}
#if !PMIC_ROHM_BD9571 #if !PMIC_ROHM_BD9571
void rcar_pwrc_system_reset(void) void rcar_pwrc_system_reset(void)
{ {
...@@ -393,6 +437,11 @@ static void __attribute__ ((section(".system_ram"))) ...@@ -393,6 +437,11 @@ static void __attribute__ ((section(".system_ram")))
self_refresh: self_refresh:
/* DFI_PHYMSTR_ACK setting */
mmio_write_32(DBSC4_REG_DBDFIPMSTRCNF,
mmio_read_32(DBSC4_REG_DBDFIPMSTRCNF) &
(~DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN));
/* Set the Self-Refresh mode */ /* Set the Self-Refresh mode */
mmio_write_32(DBSC4_REG_DBACEN, 0); mmio_write_32(DBSC4_REG_DBACEN, 0);
...@@ -633,7 +682,7 @@ void rcar_pwrc_set_suspend_to_ram(void) ...@@ -633,7 +682,7 @@ void rcar_pwrc_set_suspend_to_ram(void)
DEVICE_SRAM_STACK_SIZE); DEVICE_SRAM_STACK_SIZE);
uint32_t sctlr; uint32_t sctlr;
rcar_pwrc_save_generic_timer(rcar_stack_generic_timer); rcar_pwrc_save_timer_state();
/* disable MMU */ /* disable MMU */
sctlr = (uint32_t) read_sctlr_el3(); sctlr = (uint32_t) read_sctlr_el3();
......
drivers/renesas/rcar/pwrc/pwrc.h
View file @ 4b9d01d5
/* /*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -52,6 +52,7 @@ uint32_t rcar_pwrc_status(uint64_t mpidr); ...@@ -52,6 +52,7 @@ uint32_t rcar_pwrc_status(uint64_t mpidr);
uint32_t rcar_pwrc_get_cluster(void); uint32_t rcar_pwrc_get_cluster(void);
uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr); uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr);
uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type); uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type);
void rcar_pwrc_restore_timer_state(void);
void plat_secondary_reset(void); void plat_secondary_reset(void);
void rcar_pwrc_code_copy_to_system_ram(void); void rcar_pwrc_code_copy_to_system_ram(void);
...@@ -67,12 +68,8 @@ void rcar_pwrc_init_suspend_to_ram(void); ...@@ -67,12 +68,8 @@ void rcar_pwrc_init_suspend_to_ram(void);
void rcar_pwrc_suspend_to_ram(void); void rcar_pwrc_suspend_to_ram(void);
#endif #endif
extern void rcar_pwrc_save_generic_timer(uint64_t *rcar_stack_generic_timer);
extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack, extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack,
void *arg); void *arg);
extern uint64_t rcar_stack_generic_timer[5];
#endif #endif
#endif /* PWRC_H */ #endif /* PWRC_H */
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
View file @ 4b9d01d5
...@@ -95,7 +95,6 @@ static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; ...@@ -95,7 +95,6 @@ static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t max_density; static uint32_t max_density;
static uint32_t ddr0800_mul; static uint32_t ddr0800_mul;
static uint32_t ddr_mul; static uint32_t ddr_mul;
static uint32_t ddr_mbps;
static uint32_t DDR_PHY_SLICE_REGSET_OFS; static uint32_t DDR_PHY_SLICE_REGSET_OFS;
static uint32_t DDR_PHY_ADR_V_REGSET_OFS; static uint32_t DDR_PHY_ADR_V_REGSET_OFS;
static uint32_t DDR_PHY_ADR_I_REGSET_OFS; static uint32_t DDR_PHY_ADR_I_REGSET_OFS;
...@@ -1136,6 +1135,7 @@ static void regif_pll_wa(void) ...@@ -1136,6 +1135,7 @@ static void regif_pll_wa(void)
uint32_t ch; uint32_t ch;
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
// PLL setting for PHY : H3 Ver.1.x
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
(0x0064U << (0x0064U <<
ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
...@@ -1175,6 +1175,9 @@ static void regif_pll_wa(void) ...@@ -1175,6 +1175,9 @@ static void regif_pll_wa(void)
_reg_PHY_LP4_BOOT_TOP_PLL_CTRL)); _reg_PHY_LP4_BOOT_TOP_PLL_CTRL));
} }
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
_cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]);
/* protect register interface */ /* protect register interface */
ddrphy_regif_idle(); ddrphy_regif_idle();
pll3_control(0); pll3_control(0);
...@@ -1902,7 +1905,14 @@ static void ddr_config(void) ...@@ -1902,7 +1905,14 @@ static void ddr_config(void)
CACS DLY CACS DLY
***********************************************************************/ ***********************************************************************/
dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
set_dfifrequency(0x1f);
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
set_dfifrequency(0x1f);
} else {
ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00);
ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x01);
}
foreach_vch(ch) { foreach_vch(ch) {
int16_t adj; int16_t adj;
for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
...@@ -1921,7 +1931,13 @@ static void ddr_config(void) ...@@ -1921,7 +1931,13 @@ static void ddr_config(void)
} }
} }
} }
set_dfifrequency(0x00);
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
set_dfifrequency(0x00);
} else {
ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01);
ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x00);
}
/*********************************************************************** /***********************************************************************
WDQDM DLY WDQDM DLY
...@@ -2234,7 +2250,16 @@ static void dbsc_regset(void) ...@@ -2234,7 +2250,16 @@ static void dbsc_regset(void)
+ (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7;
if (tmp[0] < dataL) if (tmp[0] < dataL)
tmp[0] = dataL; tmp[0] = dataL;
mmio_write_32(DBSC_DBSCHRW1, tmp[0]);
if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
mmio_write_32(DBSC_DBSCHRW1, tmp[0]
+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps - 3);
} else {
mmio_write_32(DBSC_DBSCHRW1, tmp[0]
+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps);
}
/*********************************************************************** /***********************************************************************
QOS and CAM QOS and CAM
...@@ -2378,6 +2403,38 @@ static void dbsc_regset_post(void) ...@@ -2378,6 +2403,38 @@ static void dbsc_regset_post(void)
dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff)); mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff));
mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
#ifdef DDR_BACKUPMODE
if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */
PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
send_dbcmd(0x08040001);
wait_dbcmd();
send_dbcmd(0x0A040001);
wait_dbcmd();
send_dbcmd(0x04040010);
wait_dbcmd();
if (Prr_Product == PRR_PRODUCT_H3) {
send_dbcmd(0x08140001);
wait_dbcmd();
send_dbcmd(0x0A140001);
wait_dbcmd();
send_dbcmd(0x04140010);
wait_dbcmd();
}
#else /* DDR_BACKUPMODE_HALF //for All channels */
send_dbcmd(0x08840001);
wait_dbcmd();
send_dbcmd(0x0A840001);
wait_dbcmd();
send_dbcmd(0x04840010);
wait_dbcmd();
#endif /* DDR_BACKUPMODE_HALF */
}
#endif /* DDR_BACKUPMODE */
#if RCAR_REWT_TRAINING != 0 #if RCAR_REWT_TRAINING != 0
/* Periodic-WriteDQ Training seeting */ /* Periodic-WriteDQ Training seeting */
if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
...@@ -2433,37 +2490,6 @@ static void dbsc_regset_post(void) ...@@ -2433,37 +2490,6 @@ static void dbsc_regset_post(void)
#endif /* RCAR_DRAM_SPLIT == 2 */ #endif /* RCAR_DRAM_SPLIT == 2 */
} }
#ifdef DDR_BACKUPMODE
if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */
PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
send_dbcmd(0x08040001);
wait_dbcmd();
send_dbcmd(0x0A040001);
wait_dbcmd();
send_dbcmd(0x04040010);
wait_dbcmd();
if (Prr_Product == PRR_PRODUCT_H3) {
send_dbcmd(0x08140001);
wait_dbcmd();
send_dbcmd(0x0A140001);
wait_dbcmd();
send_dbcmd(0x04140010);
wait_dbcmd();
}
#else /* DDR_BACKUPMODE_HALF //for All channels */
send_dbcmd(0x08840001);
wait_dbcmd();
send_dbcmd(0x0A840001);
wait_dbcmd();
send_dbcmd(0x04840010);
wait_dbcmd();
#endif /* DDR_BACKUPMODE_HALF */
}
#endif /* DDR_BACKUPMODE */
mmio_write_32(DBSC_DBRFEN, 0x00000001); mmio_write_32(DBSC_DBRFEN, 0x00000001);
/* dram access enable */ /* dram access enable */
mmio_write_32(DBSC_DBACEN, 0x00000001); mmio_write_32(DBSC_DBACEN, 0x00000001);
...@@ -3104,6 +3130,7 @@ static uint32_t init_ddr(void) ...@@ -3104,6 +3130,7 @@ static uint32_t init_ddr(void)
/*********************************************************************** /***********************************************************************
exec pi_training exec pi_training
***********************************************************************/ ***********************************************************************/
ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00);
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
......
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
View file @ 4b9d01d5
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#define BOARDNUM 19 #define BOARDNUM 20
#define BOARD_JUDGE_AUTO #define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO #ifdef BOARD_JUDGE_AUTO
...@@ -1374,6 +1374,57 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { ...@@ -1374,6 +1374,57 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
} }
} }
}, },
/* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */
{
0x03,
0x01,
0x02c0,
0,
0x0300,
0x00a0,
{
{
{0x04, 0xff},
0x00543210,
0x3201,
{0x70612543, 0x43251670, 0x45326170, 0x10672534},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0xff},
0x00543210,
0x2310,
{0x01327654, 0x34526107, 0x35421670, 0x70615324},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
},
}; };
void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div) void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
...@@ -1618,9 +1669,12 @@ static uint32_t _board_judge(void) ...@@ -1618,9 +1669,12 @@ static uint32_t _board_judge(void)
} else if (Prr_Product == PRR_PRODUCT_M3N) { } else if (Prr_Product == PRR_PRODUCT_M3N) {
/* RENESAS SALVATOR-X (M3-N/SIP) */ /* RENESAS SALVATOR-X (M3-N/SIP) */
brd = 11; brd = 11;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20)) {
/* RENESAS SALVATOR-X (M3-W/SIP) */ /* RENESAS SALVATOR-X (M3-W/SIP) */
brd = 0; brd = 0;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W Ver.1.3/SIP) */
brd = 19;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) { } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */ /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
brd = 18; brd = 18;
......
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
View file @ 4b9d01d5
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#define RCAR_DDR_VERSION "rev.0.35rc01" #define RCAR_DDR_VERSION "rev.0.35"
#define DRAM_CH_CNT (0x04) #define DRAM_CH_CNT (0x04)
#define SLICE_CNT (0x04) #define SLICE_CNT (0x04)
#define CS_CNT (0x02) #define CS_CNT (0x02)
......
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
View file @ 4b9d01d5
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -239,8 +239,8 @@ static const uint32_t ...@@ -239,8 +239,8 @@ static const uint32_t
/*069d*/ 0x0002c000, /*069d*/ 0x0002c000,
/*069e*/ 0x02c002c0, /*069e*/ 0x02c002c0,
/*069f*/ 0x000002c0, /*069f*/ 0x000002c0,
/*06a0*/ 0x01421142, /*06a0*/ 0x03421342,
/*06a1*/ 0x00000142, /*06a1*/ 0x00000342,
/*06a2*/ 0x00000000, /*06a2*/ 0x00000000,
/*06a3*/ 0x00000000, /*06a3*/ 0x00000000,
/*06a4*/ 0x05020000, /*06a4*/ 0x05020000,
......
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
View file @ 4b9d01d5
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -219,8 +219,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = { ...@@ -219,8 +219,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
/*0b95*/ 0x0002c000, /*0b95*/ 0x0002c000,
/*0b96*/ 0x02c002c0, /*0b96*/ 0x02c002c0,
/*0b97*/ 0x000002c0, /*0b97*/ 0x000002c0,
/*0b98*/ 0x01421142, /*0b98*/ 0x03421342,
/*0b99*/ 0x00000142, /*0b99*/ 0x00000342,
/*0b9a*/ 0x00000000, /*0b9a*/ 0x00000000,
/*0b9b*/ 0x00000000, /*0b9b*/ 0x00000000,
/*0b9c*/ 0x05020000, /*0b9c*/ 0x05020000,
......
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
View file @ 4b9d01d5
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -240,8 +240,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = { ...@@ -240,8 +240,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
/*0b9e*/ 0x02c002c0, /*0b9e*/ 0x02c002c0,
/*0b9f*/ 0x000002c0, /*0b9f*/ 0x000002c0,
/*0ba0*/ 0x08040201, /*0ba0*/ 0x08040201,
/*0ba1*/ 0x01421142, /*0ba1*/ 0x03421342,
/*0ba2*/ 0x00000142, /*0ba2*/ 0x00000342,
/*0ba3*/ 0x00000000, /*0ba3*/ 0x00000000,
/*0ba4*/ 0x00000000, /*0ba4*/ 0x00000000,
/*0ba5*/ 0x05030000, /*0ba5*/ 0x05030000,
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
View file @ 4b9d01d5
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
#include "qos_init_h3_v20.h" #include "qos_init_h3_v20.h"
#define RCAR_QOS_VERSION "rev.0.20" #define RCAR_QOS_VERSION "rev.0.21"
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */ #define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
View file @ 4b9d01d5
/* /*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
#include "qos_init_h3_v30.h" #include "qos_init_h3_v30.h"
#define RCAR_QOS_VERSION "rev.0.10" #define RCAR_QOS_VERSION "rev.0.11"
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U) #define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
View file @ 4b9d01d5
/* /*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
#include "qos_init_h3n_v30.h" #include "qos_init_h3n_v30.h"
#define RCAR_QOS_VERSION "rev.0.06" #define RCAR_QOS_VERSION "rev.0.07"
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U) #define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
View file @ 4b9d01d5
/* /*
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
#include "../qos_reg.h" #include "../qos_reg.h"
#include "qos_init_m3_v11.h" #include "qos_init_m3_v11.h"
#define RCAR_QOS_VERSION "rev.0.18" #define RCAR_QOS_VERSION "rev.0.19"
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */ #define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
......
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
View file @ 4b9d01d5
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
#include "../qos_reg.h" #include "../qos_reg.h"
#include "qos_init_m3_v30.h" #include "qos_init_m3_v30.h"
#define RCAR_QOS_VERSION "rev.0.1" #define RCAR_QOS_VERSION "rev.0.02"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U) #define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U) #define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
View file @ 4b9d01d5
/* /*
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
#include "../qos_reg.h" #include "../qos_reg.h"
#include "qos_init_m3n_v10.h" #include "qos_init_m3n_v10.h"
#define RCAR_QOS_VERSION "rev.0.08" #define RCAR_QOS_VERSION "rev.0.09"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U) #define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U) #define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......
drivers/staging/renesas/rcar/qos/qos_common.h
View file @ 4b9d01d5
...@@ -34,9 +34,9 @@ ...@@ -34,9 +34,9 @@
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
/* define used for M3N */ /* define used for M3N */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
#define SUB_SLOT_CYCLE_M3N (0x84U) /* 132 */ #define SUB_SLOT_CYCLE_M3N (0x7EU) /* 126 */
#else /* REF 3.9usec */ #else /* REF 3.9usec */
#define SUB_SLOT_CYCLE_M3N (0x108U) /* 264 */ #define SUB_SLOT_CYCLE_M3N (0xFCU) /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U) #define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U)
...@@ -46,9 +46,9 @@ ...@@ -46,9 +46,9 @@
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
/* define used for H3 */ /* define used for H3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
#define SUB_SLOT_CYCLE_H3_20 (0x84U) /* 132 */ #define SUB_SLOT_CYCLE_H3_20 (0x7EU) /* 126 */
#else /* REF 3.9usec */ #else /* REF 3.9usec */
#define SUB_SLOT_CYCLE_H3_20 (0x108U) /* 264 */ #define SUB_SLOT_CYCLE_H3_20 (0xFCU) /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U) #define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U)
...@@ -64,9 +64,9 @@ ...@@ -64,9 +64,9 @@
#if (RCAR_LSI == RCAR_H3N) #if (RCAR_LSI == RCAR_H3N)
/* define used for H3N */ /* define used for H3N */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
#define SUB_SLOT_CYCLE_H3N (0x84U) /* 132 */ #define SUB_SLOT_CYCLE_H3N (0x7EU) /* 126 */
#else /* REF 3.9usec */ #else /* REF 3.9usec */
#define SUB_SLOT_CYCLE_H3N (0x108U) /* 264 */ #define SUB_SLOT_CYCLE_H3N (0xFCU) /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U) #define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U)
...@@ -77,11 +77,11 @@ ...@@ -77,11 +77,11 @@
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
/* define used for M3 */ /* define used for M3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
#define SUB_SLOT_CYCLE_M3_11 (0x84U) /* 132 */ #define SUB_SLOT_CYCLE_M3_11 (0x7EU) /* 126 */
#define SUB_SLOT_CYCLE_M3_30 (0x84U) /* 132 */ #define SUB_SLOT_CYCLE_M3_30 (0x7EU) /* 126 */
#else /* REF 3.9usec */ #else /* REF 3.9usec */
#define SUB_SLOT_CYCLE_M3_11 (0x108U) /* 264 */ #define SUB_SLOT_CYCLE_M3_11 (0xFCU) /* 252 */
#define SUB_SLOT_CYCLE_M3_30 (0x108U) /* 264 */ #define SUB_SLOT_CYCLE_M3_30 (0xFCU) /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U) #define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
......
plat/renesas/rcar/include/rcar_version.h
View file @ 4b9d01d5
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#include <arch_helpers.h> #include <arch_helpers.h>
#define VERSION_OF_RENESAS "2.0.1" #define VERSION_OF_RENESAS "2.0.3"
#define VERSION_OF_RENESAS_MAXLEN (128) #define VERSION_OF_RENESAS_MAXLEN (128)
extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]; extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
......
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