juno: Update GIC addresses

Signed-off-by: Jon Medhurst <tixy@linaro.org>

plat/juno/plat_gic.c

@@ -59,7 +59,7 @@ void gicv3_cpuif_setup(void)
 	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
 	 * per CPU.
 	 */
-	base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr());
+	base = gicv3_get_rdist(GICR_BASE, read_mpidr());
 	if (base == (uintptr_t)NULL) {
 		/* No re-distributor base address. This interface cannot be
 		 * configured.
@@ -123,7 +123,7 @@ void gicv3_cpuif_deactivate(void)
 	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
 	 * per CPU.
 	 */
-	base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr());
+	base = gicv3_get_rdist(GICR_BASE, read_mpidr());
 	if (base == (uintptr_t)NULL) {
 		/* No re-distributor base address. This interface cannot be
 		 * configured.
@@ -272,11 +272,6 @@ void gic_distif_setup(unsigned int gicd_base)
 
 void gic_setup(void)
 {
-	unsigned int gicd_base, gicc_base;
-
-	gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
-	gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
-
-	gic_cpuif_setup(gicc_base);
-	gic_distif_setup(gicd_base);
+	gic_cpuif_setup(GICC_BASE);
+	gic_distif_setup(GICD_BASE);
 }

plat/juno/platform.h

@@ -171,20 +171,12 @@
 /*******************************************************************************
  * GIC-400 & interrupt handling related constants
  ******************************************************************************/
-/* VE compatible GIC memory map */
-#define VE_GICD_BASE			0x2c001000
-#define VE_GICC_BASE			0x2c002000
-#define VE_GICH_BASE			0x2c004000
-#define VE_GICV_BASE			0x2c006000
-
-/* Base FVP compatible GIC memory map */
-#define BASE_GICD_BASE			0x2f000000
-#define BASE_GICR_BASE			0x2f100000
-#define BASE_GICC_BASE			0x2c000000
-#define BASE_GICH_BASE			0x2c010000
-#define BASE_GICV_BASE			0x2c02f000
-
-#define IRQ_TZ_WDOG			56
+#define GICD_BASE			0x2c010000
+#define GICC_BASE			0x2c02f000
+#define GICH_BASE			0x2c04f000
+#define GICV_BASE			0x2c06f000
+
+#define IRQ_TZ_WDOG			86
 #define IRQ_SEC_PHY_TIMER		29
 #define IRQ_SEC_SGI_0			8
 #define IRQ_SEC_SGI_1			9