Merge changes from topic "tegra-downstream-092319" into integration

* changes:
  Tegra194: add support to reset GPU
  Tegra194: memctrl: fix logic to check TZDRAM config register access
  Tegra: introduce plat_enable_console()
  Tegra: include: drivers: introduce spe.h
  Tegra194: update nvg header to v6.4
  Tegra194: mce: enable strict checking
  Tegra194: CC6 state from last offline CPU in the cluster
  Tegra194: console driver compilation from platform makefiles
  Tegra194: memctrl: platform handler for TZDRAM setup
  Tegra194: memctrl: override SE client as coherent
  Tegra194: save system suspend entry marker to TZDRAM
  Tegra194: helper functions for CPU rst handler and SMMU ctx offset
  Tegra194: cleanup references to Tegra186
  Tegra194: mce: display NVG header version during boot
  Tegra194: mce: fix cg_cstate encoding format
  Tegra194: drivers: SE and RNG1/PKA1 context save support
  Tegra194: rename secure scratch register macros
  Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation
  Tegra194: mce: remove unsupported functionality
  Tegra194: sanity check target cluster during core power on
  Tegra194: fix defects flagged by MISRA scan
  Tegra194: mce: fix defects flagged by MISRA scan
  Tegra194: remove the GPU reset register macro
  Tegra194: MC registers to allow CPU accesses to TZRAM
  Tegra194: increase MAX_MMAP_REGIONS macro value
  Tegra194: update nvg header to v6.1
  Tegra194: update cache operations supported by the ROC
  Tegra194: memctrl: platform handlers to reprogram MSS
  Tegra194: core and cluster count values
  Tegra194: correct the TEGRA_CAR_RESET_BASE macro value
  Tegra194: add MC_SECURITY mask defines
  Tegra194: Update wake mask, wake time for cpu offlining
  Tegra194: program stream ids for XUSB
  Tegra194: Update checks for c-state stats
  Tegra194: smmu: fix mask for board revision id
  Tegra194: smmu: ISO support
  Tegra194: Initialize smmu on system suspend exit
  Tegra194: Update cpu core-id calculation
  Tegra194: read-modify-write ACTLR_ELx registers
  Tegra194: Enable fake system suspend
  Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
  Tegra194: platform support for memctrl/smmu drivers
  Tegra194: Support for cpu suspend

plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h → plat/nvidia/tegra/soc/t194/plat_smmu.c

@@ -4,14 +4,25 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __SMMU_PLAT_CONFIG_H
-#define __SMMU_PLAT_CONFIG_H
-
-#include <mmio.h>
-#include <tegra_def.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
 #include <smmu.h>
+#include <tegra_def.h>
+#include <tegra_mc_def.h>
 
-static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
+#define BOARD_SYSTEM_FPGA_BASE		U(1)
+#define BASE_CONFIG_SMMU_DEVICES	U(2)
+#define MAX_NUM_SMMU_DEVICES		U(3)
+
+static uint32_t tegra_misc_read_32(uint32_t off)
+{
+	return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off);
+}
+
+/*******************************************************************************
+ * Array to hold SMMU context for Tegra194
+ ******************************************************************************/
+static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
 	_START_OF_TABLE_,
 	mc_make_sid_security_cfg(HDAR),
 	mc_make_sid_security_cfg(HOST1XDMAR),
@@ -400,29 +411,29 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
 	_END_OF_TABLE_,
 };
 
-static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
+/*******************************************************************************
+ * Handler to return the pointer to the SMMU's context struct
+ ******************************************************************************/
+smmu_regs_t *plat_get_smmu_ctx(void)
 {
-	if (smmu_id == 0)
-		return mmio_read_32(TEGRA_SMMU0_BASE + off);
-	else if (smmu_id == 1)
-		return mmio_read_32(TEGRA_SMMU1_BASE + off);
-	else if (smmu_id == 2)
-		return mmio_read_32(TEGRA_SMMU2_BASE + off);
-	else
-		panic();
+	/* index of _END_OF_TABLE_ */
+	tegra194_smmu_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_smmu_context) - 1U;
+
+	return tegra194_smmu_context;
 }
 
-static inline void tegra_smmu_write_32(uint32_t smmu_id,
-			uint32_t off, uint32_t val)
+/*******************************************************************************
+ * Handler to return the support SMMU devices number
+ ******************************************************************************/
+uint32_t plat_get_num_smmu_devices(void)
 {
-	if (smmu_id == 0)
-		mmio_write_32(TEGRA_SMMU0_BASE + off, val);
-	else if (smmu_id == 1)
-		mmio_write_32(TEGRA_SMMU1_BASE + off, val);
-	else if (smmu_id == 2)
-		mmio_write_32(TEGRA_SMMU2_BASE + off, val);
-	else
-		panic();
-}
+	uint32_t ret_num = MAX_NUM_SMMU_DEVICES;
+	uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \
+							BOARD_SHIFT_BITS) & BOARD_MASK_BITS);
 
-#endif //__SMMU_PLAT_CONFIG_H
+	if (board_revid == BOARD_SYSTEM_FPGA_BASE) {
+		ret_num = BASE_CONFIG_SMMU_DEVICES;
+	}
+
+	return ret_num;
+}

plat/nvidia/tegra/soc/t194/plat_trampoline.S

@@ -10,27 +10,36 @@
 #include <memctrl_v2.h>
 #include <tegra_def.h>
 
-#define TEGRA186_SMMU_CTX_SIZE		0x490
+#define TEGRA194_STATE_SYSTEM_SUSPEND	0x5C7
+#define TEGRA194_STATE_SYSTEM_RESUME	0x600D
+#define TEGRA194_SMMU_CTX_SIZE		0x490
 
 	.align 4
-	.globl	tegra186_cpu_reset_handler
+	.globl	tegra194_cpu_reset_handler
 
 /* CPU reset handler routine */
-func tegra186_cpu_reset_handler
-	/*
-	 * The TZRAM loses state during System Suspend. We use this
-	 * information to decide if the reset handler is running after a
-	 * System Suspend. Resume from system suspend requires restoring
-	 * the entire state from TZDRAM to TZRAM.
-	 */
-	mov	x0, #BL31_BASE
-	ldr	x0, [x0]
-	cbnz	x0, boot_cpu
+func tegra194_cpu_reset_handler
+	/* check if we are exiting system suspend state */
+	adr	x0, __tegra194_system_suspend_state
+	ldr	x1, [x0]
+	mov	x2, #TEGRA194_STATE_SYSTEM_SUSPEND
+	lsl	x2, x2, #16
+	add	x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
+	cmp	x1, x2
+	bne	boot_cpu
 
-	/* resume from system suspend */
+	/* set system resume state */
+	mov	x1, #TEGRA194_STATE_SYSTEM_RESUME
+	lsl	x1, x1, #16
+	mov	x2, #TEGRA194_STATE_SYSTEM_RESUME
+	add	x1, x1, x2
+	str	x1, [x0]
+	dsb	sy
+
+	/* prepare to relocate to TZSRAM */
 	mov	x0, #BL31_BASE
-	adr	x1, __tegra186_cpu_reset_handler_end
-	adr	x2, __tegra186_cpu_reset_handler_data
+	adr	x1, __tegra194_cpu_reset_handler_end
+	adr	x2, __tegra194_cpu_reset_handler_data
 	ldr	x2, [x2, #8]
 
 	/* memcpy16 */
@@ -50,13 +59,13 @@ m_loop1:
 	b.ne	m_loop1
 
 boot_cpu:
-	adr	x0, __tegra186_cpu_reset_handler_data
+	adr	x0, __tegra194_cpu_reset_handler_data
 	ldr	x0, [x0]
 	br	x0
-endfunc tegra186_cpu_reset_handler
+endfunc tegra194_cpu_reset_handler
 
 	/*
-	 * Tegra186 reset data (offset 0x0 - 0x2490)
+	 * Tegra194 reset data (offset 0x0 - 0x2490)
 	 *
 	 * 0x0000: secure world's entrypoint
 	 * 0x0008: BL31 size (RO + RW)
@@ -65,19 +74,71 @@ endfunc tegra186_cpu_reset_handler
 	 */
 
 	.align 4
-	.type	__tegra186_cpu_reset_handler_data, %object
-	.globl	__tegra186_cpu_reset_handler_data
-__tegra186_cpu_reset_handler_data:
+	.type	__tegra194_cpu_reset_handler_data, %object
+	.globl	__tegra194_cpu_reset_handler_data
+__tegra194_cpu_reset_handler_data:
 	.quad	tegra_secure_entrypoint
 	.quad	__BL31_END__ - BL31_BASE
-	.globl	__tegra186_smmu_ctx_start
-__tegra186_smmu_ctx_start:
-	.rept	TEGRA186_SMMU_CTX_SIZE
+
+	.globl	__tegra194_system_suspend_state
+__tegra194_system_suspend_state:
+	.quad	0
+
+	.align 4
+__tegra194_smmu_context:
+	.rept	TEGRA194_SMMU_CTX_SIZE
 	.quad	0
 	.endr
-	.size	__tegra186_cpu_reset_handler_data, \
-		. - __tegra186_cpu_reset_handler_data
+	.size	__tegra194_cpu_reset_handler_data, \
+		. - __tegra194_cpu_reset_handler_data
 
 	.align 4
-	.globl	__tegra186_cpu_reset_handler_end
-__tegra186_cpu_reset_handler_end:
+	.globl	__tegra194_cpu_reset_handler_end
+__tegra194_cpu_reset_handler_end:
+
+	.globl tegra194_get_cpu_reset_handler_size
+	.globl tegra194_get_cpu_reset_handler_base
+	.globl tegra194_get_smmu_ctx_offset
+	.globl tegra194_set_system_suspend_entry
+
+/* return size of the CPU reset handler */
+func tegra194_get_cpu_reset_handler_size
+	adr	x0, __tegra194_cpu_reset_handler_end
+	adr	x1, tegra194_cpu_reset_handler
+	sub	x0, x0, x1
+	ret
+endfunc tegra194_get_cpu_reset_handler_size
+
+/* return the start address of the CPU reset handler */
+func tegra194_get_cpu_reset_handler_base
+	adr	x0, tegra194_cpu_reset_handler
+	ret
+endfunc tegra194_get_cpu_reset_handler_base
+
+/* return the size of the SMMU context */
+func tegra194_get_smmu_ctx_offset
+	adr	x0, __tegra194_smmu_context
+	adr	x1, tegra194_cpu_reset_handler
+	sub	x0, x0, x1
+	ret
+endfunc tegra194_get_smmu_ctx_offset
+
+/* set system suspend state before SC7 entry */
+func tegra194_set_system_suspend_entry
+	mov	x0, #TEGRA_MC_BASE
+	mov	x3, #MC_SECURITY_CFG3_0
+	ldr	w1, [x0, x3]
+	lsl	x1, x1, #32
+	mov	x3, #MC_SECURITY_CFG0_0
+	ldr	w2, [x0, x3]
+	orr	x3, x1, x2			/* TZDRAM base */
+	adr	x0, __tegra194_system_suspend_state
+	adr	x1, tegra194_cpu_reset_handler
+	sub	x2, x0, x1			/* offset in TZDRAM */
+	mov	x0, #TEGRA194_STATE_SYSTEM_SUSPEND
+	lsl	x0, x0, #16
+	add	x0, x0, #TEGRA194_STATE_SYSTEM_SUSPEND
+	str	x0, [x3, x2]			/* set value in TZDRAM */
+	dsb	sy
+	ret
+endfunc tegra194_set_system_suspend_entry

plat/nvidia/tegra/soc/t194/platform_t194.mk

@@ -5,15 +5,12 @@
 #
 
 # platform configs
-ENABLE_AFI_DEVICE			:= 0
-$(eval $(call add_define,ENABLE_AFI_DEVICE))
+ENABLE_CONSOLE_SPE			:= 0
+$(eval $(call add_define,ENABLE_CONSOLE_SPE))
 
 ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS	:= 0
 $(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
 
-ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM	:= 1
-$(eval $(call add_define,ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM))
-
 RELOCATE_TO_BL31_BASE			:= 1
 $(eval $(call add_define,RELOCATE_TO_BL31_BASE))
 
@@ -23,9 +20,6 @@ $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
 ENABLE_SMMU_DEVICE			:= 1
 $(eval $(call add_define,ENABLE_SMMU_DEVICE))
 
-NUM_SMMU_DEVICES			:= 3
-$(eval $(call add_define,NUM_SMMU_DEVICES))
-
 RESET_TO_BL31				:= 1
 
 PROGRAMMABLE_RESET_ADDRESS		:= 1
@@ -36,32 +30,37 @@ COLD_BOOT_SINGLE_CPU			:= 1
 TZDRAM_BASE				:= 0x40000000
 $(eval $(call add_define,TZDRAM_BASE))
 
-PLATFORM_CLUSTER_COUNT			:= 2
+PLATFORM_CLUSTER_COUNT			:= 4
 $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
 
-PLATFORM_MAX_CPUS_PER_CLUSTER		:= 4
+PLATFORM_MAX_CPUS_PER_CLUSTER		:= 2
 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
 
-MAX_XLAT_TABLES				:= 24
+MAX_XLAT_TABLES				:= 25
 $(eval $(call add_define,MAX_XLAT_TABLES))
 
-MAX_MMAP_REGIONS			:= 24
+MAX_MMAP_REGIONS			:= 30
 $(eval $(call add_define,MAX_MMAP_REGIONS))
 
 # platform files
 PLAT_INCLUDES		+=	-I${SOC_DIR}/drivers/include
 
-BL31_SOURCES		+=	lib/cpus/aarch64/denver.S		\
+BL31_SOURCES		+=	drivers/ti/uart/aarch64/16550_console.S \
+				lib/cpus/aarch64/denver.S		\
 				${COMMON_DIR}/drivers/memctrl/memctrl_v2.c	\
 				${COMMON_DIR}/drivers/smmu/smmu.c	\
 				${SOC_DIR}/drivers/mce/mce.c		\
 				${SOC_DIR}/drivers/mce/nvg.c		\
 				${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
+				${SOC_DIR}/drivers/se/se.c		\
+				${SOC_DIR}/plat_memctrl.c		\
 				${SOC_DIR}/plat_psci_handlers.c		\
 				${SOC_DIR}/plat_setup.c			\
 				${SOC_DIR}/plat_secondary.c		\
-				${SOC_DIR}/plat_sip_calls.c
+				${SOC_DIR}/plat_sip_calls.c		\
+				${SOC_DIR}/plat_smmu.c			\
+				${SOC_DIR}/plat_trampoline.S
 
-ifeq (${ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM}, 1)
-BL31_SOURCES		+=	${SOC_DIR}/plat_trampoline.S
+ifeq (${ENABLE_CONSOLE_SPE},1)
+BL31_SOURCES		+=	${COMMON_DIR}/drivers/spe/shared_console.S
 endif

plat/nvidia/tegra/soc/t210/plat_setup.c

@@ -114,14 +114,30 @@ static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = {
 };
 
 /*******************************************************************************
- * Retrieve the UART controller base to be used as the console
+ * Enable console corresponding to the console ID
  ******************************************************************************/
-uint32_t plat_get_console_from_id(int id)
+void plat_enable_console(int32_t id)
 {
-	if (id > TEGRA210_MAX_UART_PORTS)
-		return 0;
+	static console_16550_t uart_console;
+	uint32_t console_clock;
 
-	return tegra210_uart_addresses[id];
+	if ((id > 0) && (id < TEGRA210_MAX_UART_PORTS)) {
+		/*
+		 * Reference clock used by the FPGAs is a lot slower.
+		 */
+		if (tegra_platform_is_fpga()) {
+			console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+		} else {
+			console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+		}
+
+		(void)console_16550_register(tegra210_uart_addresses[id],
+					     console_clock,
+					     TEGRA_CONSOLE_BAUDRATE,
+					     &uart_console);
+		console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
+			CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+	}
 }
 
 /*******************************************************************************