FVP: Change BL31_BASE when RESET_TO_BL31=1

This patch defines BL31_BASE to 0x0 when RESET_TO_BL31=1 as the
executable is built with PIE support and can be loaded anywhere
in SRAM for execution.

Change-Id: I4007f4626322f1200a6304c9c565987d3357986c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

include/plat/arm/common/arm_def.h

@@ -407,12 +407,16 @@
 #define BL31_LIMIT			(ARM_AP_TZC_DRAM1_BASE +	\
 						PLAT_ARM_MAX_BL31_SIZE)
 #elif (RESET_TO_BL31)
+/* Ensure Position Independent support (PIE) is enabled for this config.*/
+# if !ENABLE_PIE
+#  error "BL31 must be a PIE if RESET_TO_BL31=1."
+# endif
 /*
- * Put BL31_BASE in the middle of the Trusted SRAM.
+ * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
+ * used for building BL31 when RESET_TO_BL31=1.
  */
-#define BL31_BASE			(ARM_TRUSTED_SRAM_BASE + \
-						(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
-#define BL31_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+#define BL31_BASE			0x0
+#define BL31_LIMIT			PLAT_ARM_MAX_BL31_SIZE
 #else
 /* Put BL31 below BL2 in the Trusted SRAM.*/
 #define BL31_BASE			((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\