Unverified Commit 6ab136c2 authored by Dimitris Papastamos's avatar Dimitris Papastamos Committed by GitHub
Browse files

Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements

Fix switch statements to comply with MISRA rules
parents 875a85aa 185a23ff
......@@ -87,6 +87,7 @@ register_t bl1_fwu_smc_handler(unsigned int smc_fid,
case FWU_SMC_UPDATE_DONE:
bl1_fwu_done((void *)x1, NULL);
/* We should never return from bl1_fwu_done() */
break;
default:
assert(0);
......@@ -747,6 +748,7 @@ static int bl1_fwu_image_reset(unsigned int image_id, unsigned int flags)
case IMAGE_STATE_EXECUTED:
default:
assert(0);
break;
}
return 0;
......
......@@ -83,22 +83,25 @@ static unsigned int read_cci_part_number(uintptr_t base)
*/
static int get_slave_ports(unsigned int part_num)
{
/* Macro to match CCI products */
#define RET_ON_MATCH(product) \
case CCI ## product ## _PART_NUM: \
return CCI ## product ## _SLAVE_PORTS
int num_slave_ports = -1;
switch (part_num) {
RET_ON_MATCH(400);
RET_ON_MATCH(500);
RET_ON_MATCH(550);
case CCI400_PART_NUM:
num_slave_ports = CCI400_SLAVE_PORTS;
break;
case CCI500_PART_NUM:
num_slave_ports = CCI500_SLAVE_PORTS;
break;
case CCI550_PART_NUM:
num_slave_ports = CCI550_SLAVE_PORTS;
break;
default:
return -1;
/* Do nothing in default case */
break;
}
#undef RET_ON_MATCH
return num_slave_ports;
}
#endif /* ENABLE_ASSERTIONS */
......
......@@ -459,6 +459,7 @@ void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
break;
default:
assert(0);
break;
}
spin_unlock(&gic_lock);
}
......
......@@ -1004,6 +1004,7 @@ void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
break;
default:
assert(0);
break;
}
if (id < MIN_SPI_ID) {
......
......@@ -321,6 +321,7 @@ static int dw_set_ios(int clk, int width)
break;
default:
assert(0);
break;
}
dw_set_clk(clk);
return 0;
......
......@@ -271,6 +271,7 @@ static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun,
break;
default:
assert(0);
break;
}
if (hd->dd == DD_IN)
flush_dcache_range(buf, length);
......@@ -359,6 +360,7 @@ static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn,
break;
default:
assert(0);
break;
}
flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t));
flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
......@@ -511,6 +513,9 @@ static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel,
case QUERY_WRITE_ATTR:
assert(((buf & 3) == 0) && (size != 0));
break;
default:
/* Do nothing in default case */
break;
}
get_utrd(&utrd);
ufs_prepare_query(&utrd, op, idn, index, sel, buf, size);
......@@ -533,6 +538,9 @@ static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel,
(void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)),
size);
break;
default:
/* Do nothing in default case */
break;
}
(void)result;
}
......
......@@ -37,8 +37,8 @@
/*
* Defines for PMF SMC function ids.
*/
#define PMF_SMC_GET_TIMESTAMP_32 0x82000010
#define PMF_SMC_GET_TIMESTAMP_64 0xC2000010
#define PMF_SMC_GET_TIMESTAMP_32 0x82000010u
#define PMF_SMC_GET_TIMESTAMP_64 0xC2000010u
#define PMF_NUM_SMC_CALLS 2
/*
......
......@@ -30,8 +30,7 @@ uintptr_t pmf_smc_handler(unsigned int smc_fid,
x2 = (uint32_t)x2;
x3 = (uint32_t)x3;
switch (smc_fid) {
case PMF_SMC_GET_TIMESTAMP_32:
if (smc_fid == PMF_SMC_GET_TIMESTAMP_32) {
/*
* Return error code and the captured
* time-stamp to the caller.
......@@ -41,13 +40,9 @@ uintptr_t pmf_smc_handler(unsigned int smc_fid,
rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value);
SMC_RET3(handle, rc, (uint32_t)ts_value,
(uint32_t)(ts_value >> 32));
default:
break;
}
} else {
switch (smc_fid) {
case PMF_SMC_GET_TIMESTAMP_64:
if (smc_fid == PMF_SMC_GET_TIMESTAMP_64) {
/*
* Return error code and the captured
* time-stamp to the caller.
......@@ -56,9 +51,6 @@ uintptr_t pmf_smc_handler(unsigned int smc_fid,
*/
rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value);
SMC_RET2(handle, rc, ts_value);
default:
break;
}
}
......
......@@ -414,10 +414,12 @@ u_register_t psci_smc_handler(uint32_t smc_fid,
case PSCI_SYSTEM_OFF:
psci_system_off();
/* We should never return from psci_system_off() */
break;
case PSCI_SYSTEM_RESET:
psci_system_reset();
/* We should never return from psci_system_reset() */
break;
case PSCI_FEATURES:
return psci_features(x1);
......
......@@ -324,13 +324,11 @@ static int fvp_node_hw_state(u_register_t target_cpu,
if (psysr == PSYSR_INVALID)
return PSCI_E_INVALID_PARAMS;
switch (power_level) {
case ARM_PWR_LVL0:
if (power_level == ARM_PWR_LVL0) {
ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF;
break;
case ARM_PWR_LVL1:
} else {
/* power_level == ARM_PWR_LVL1 */
ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF;
break;
}
return ret;
......
......@@ -305,6 +305,9 @@ int arm_bl2_handle_post_image_load(unsigned int image_id)
}
break;
#endif
default:
/* Do nothing in default case */
break;
}
return err;
......
......@@ -190,6 +190,8 @@ void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority)
int plat_ic_has_interrupt_type(unsigned int type)
{
int has_interrupt_type = 0;
switch (type) {
#if GICV2_G0_FOR_EL3
case INTR_TYPE_EL3:
......@@ -197,10 +199,14 @@ int plat_ic_has_interrupt_type(unsigned int type)
case INTR_TYPE_S_EL1:
#endif
case INTR_TYPE_NS:
return 1;
has_interrupt_type = 1;
break;
default:
return 0;
/* Do nothing in default case */
break;
}
return has_interrupt_type;
}
void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
......@@ -221,6 +227,7 @@ void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
break;
default:
assert(0);
break;
}
gicv2_set_interrupt_type(id, gicv2_type);
......@@ -260,6 +267,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
break;
default:
assert(0);
break;
}
gicv2_set_spi_routing(id, proc_num);
......
......@@ -158,15 +158,14 @@ uint32_t plat_interrupt_type_to_line(uint32_t type,
return __builtin_ctz(SCR_FIQ_BIT);
else
return __builtin_ctz(SCR_IRQ_BIT);
default:
assert(0);
/* Fall through in the release build */
case INTR_TYPE_EL3:
/*
* The EL3 interrupts are signaled as FIQ in both S-EL0/1 and
* NS-EL0/1/2 contexts
*/
return __builtin_ctz(SCR_FIQ_BIT);
default:
panic();
}
}
......@@ -248,6 +247,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
break;
default:
assert(0);
break;
}
gicv3_set_spi_routing(id, irm, mpidr);
......
......@@ -175,6 +175,9 @@ int hikey_bl2_handle_post_image_load(unsigned int image_id)
}
break;
#endif
default:
/* Do nothing in default case */
break;
}
return err;
......
......@@ -267,6 +267,9 @@ int hikey960_bl2_handle_post_image_load(unsigned int image_id)
}
break;
#endif
default:
/* Do nothing in default case */
break;
}
return err;
......
......@@ -193,6 +193,9 @@ int poplar_bl2_handle_post_image_load(unsigned int image_id)
}
break;
#endif
default:
/* Do nothing in default case */
break;
}
return err;
......
......@@ -41,15 +41,8 @@ uint64_t oem_smc_handler(uint32_t smc_fid,
void *handle,
uint64_t flags)
{
uint64_t rc;
switch (smc_fid) {
default:
rc = SMC_UNK;
WARN("Unimplemented OEM Call: 0x%x\n", smc_fid);
}
SMC_RET1(handle, rc);
WARN("Unimplemented OEM Call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
/*
......
......@@ -71,6 +71,9 @@ uint64_t mediatek_sip_handler(uint32_t smc_fid,
boot_to_kernel(x1, x2, x3, x4);
SMC_RET0(handle);
#endif
default:
/* Do nothing in default case */
break;
}
}
......
......@@ -287,6 +287,9 @@ static int qemu_bl2_handle_post_image_load(unsigned int image_id)
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
break;
default:
/* Do nothing in default case */
break;
}
return err;
......
......@@ -59,13 +59,11 @@ uint64_t sip_smc_handler(uint32_t smc_fid,
case SIP_SVC_UID:
/* Return UID to the caller */
SMC_UUID_RET(handle, rk_sip_svc_uid);
break;
case SIP_SVC_VERSION:
/* Return the version of current implementation */
SMC_RET2(handle, RK_SIP_SVC_VERSION_MAJOR,
RK_SIP_SVC_VERSION_MINOR);
break;
default:
return rockchip_plat_sip_handler(smc_fid, x1, x2, x3, x4,
......
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