CPU: Correct names of implementation-defined aux regs

At present, various CPU register macros that refer to CPUACTLR are named ACTLR. This patch fixes that. The previous register names are retained, but guarded by the ERROR_DEPRECATED macro, so as not to break platforms that continue using the old names. Change-Id: Ia872196d81803f8f390b887d149e0fd054df519b Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>

CPU: Correct names of implementation-defined aux regs
At present, various CPU register macros that refer to CPUACTLR are named ACTLR. This patch fixes that. The previous register names are retained, but guarded by the ERROR_DEPRECATED macro, so as not to break platforms that continue using the old names. Change-Id: Ia872196d81803f8f390b887d149e0fd054df519b Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
80bcf981 · Eleanor Bonnici · Jeenu Viswambharan · e4e6c4be · 80bcf981 · 80bcf981
Commit 80bcf981 authored Aug 09, 2017 by Eleanor Bonnici Committed by Jeenu Viswambharan Aug 29, 2017
--- a/include/lib/cpus/aarch32/cortex_a53.h
+++ b/include/lib/cpus/aarch32/cortex_a53.h
@@ -40,11 +40,11 @@
 /*******************************************************************************
 * CPU Auxiliary Control register specific definitions.
 ******************************************************************************/
-#define CORTEX_A53_ACTLR			p15, 0, c15
+#define CORTEX_A53_CPUACTLR			p15, 0, c15
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	44
+#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT	44
-#define CORTEX_A53_ACTLR_ENDCCASCI		(1 << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
+#define CORTEX_A53_CPUACTLR_ENDCCASCI		(1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
-#define CORTEX_A53_ACTLR_DTAH			(1 << 24)
+#define CORTEX_A53_CPUACTLR_DTAH		(1 << 24)
 /*******************************************************************************
 * L2 Auxiliary Control register specific definitions.
@@ -67,4 +67,16 @@
 ******************************************************************************/
 #define CORTEX_A53_L2MERRSR			p15, 3, c15
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A53_ACTLR			CORTEX_A53_CPUACTLR
+#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT
+#define CORTEX_A53_ACTLR_ENDCCASCI		CORTEX_A53_CPUACTLR_ENDCCASCI
+#define CORTEX_A53_ACTLR_DTAH			CORTEX_A53_CPUACTLR_DTAH
+#endif /* !ERROR_DEPRECATED */
 #endif /* __CORTEX_A53_H__ */
--- a/include/lib/cpus/aarch32/cortex_a57.h
+++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -41,17 +41,17 @@
 /*******************************************************************************
 * CPU Auxiliary Control register specific definitions.
 ******************************************************************************/
-#define CORTEX_A57_ACTLR			p15, 0, c15
+#define CORTEX_A57_CPUACTLR				p15, 0, c15
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	(ULL(1) << 59)
+#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB		(ULL(1) << 59)
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	(ULL(1) << 54)
+#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE		(ULL(1) << 54)
-#define CORTEX_A57_ACTLR_DIS_OVERREAD		(ULL(1) << 52)
+#define CORTEX_A57_CPUACTLR_DIS_OVERREAD		(ULL(1) << 52)
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
+#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI		(ULL(1) << 44)
+#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI			(ULL(1) << 44)
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	(ULL(1) << 38)
+#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH		(ULL(1) << 38)
-#define CORTEX_A57_ACTLR_DIS_STREAMING		(ULL(3) << 27)
+#define CORTEX_A57_CPUACTLR_DIS_STREAMING		(ULL(3) << 27)
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	(ULL(3) << 25)
+#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING		(ULL(3) << 25)
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	(ULL(1) << 4)
+#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR	(ULL(1) << 4)
 /*******************************************************************************
 * L2 Control register specific definitions.
@@ -77,4 +77,22 @@
 ******************************************************************************/
 #define CORTEX_A57_L2MERRSR			p15, 3, c15
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A57_ACTLR			CORTEX_A57_CPUACTLR
+#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
+#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
+#define CORTEX_A57_ACTLR_DIS_OVERREAD		CORTEX_A57_CPUACTLR_DIS_OVERREAD
+#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
+#define CORTEX_A57_ACTLR_DCC_AS_DCCI		CORTEX_A57_CPUACTLR_DCC_AS_DCCI
+#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
+#define CORTEX_A57_ACTLR_DIS_STREAMING		CORTEX_A57_CPUACTLR_DIS_STREAMING
+#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	CORTEX_A57_CPUACTLR_DIS_L1_STREAMING
+#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
+#endif /* !ERROR_DEPRECATED */
 #endif /* __CORTEX_A57_H__ */
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -29,11 +29,11 @@
 /*******************************************************************************
 * CPU Auxiliary Control register specific definitions.
 ******************************************************************************/
-#define CORTEX_A72_ACTLR				p15, 0, c15
+#define CORTEX_A72_CPUACTLR				p15, 0, c15
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
+#define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			(ULL(1) << 49)
+#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI			(ULL(1) << 44)
+#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI			(ULL(1) << 44)
 /*******************************************************************************
 * L2 Control register specific definitions.
@@ -52,4 +52,16 @@
 ******************************************************************************/
 #define CORTEX_A72_L2MERRSR				p15, 3, c15
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A72_ACTLR				CORTEX_A72_CPUACTLR
+#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
+#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA
+#define CORTEX_A72_ACTLR_DCC_AS_DCCI			CORTEX_A72_CPUACTLR_DCC_AS_DCCI
+#endif /* !ERROR_DEPRECATED */
 #endif /* __CORTEX_A72_H__ */
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -40,16 +40,16 @@
 /*******************************************************************************
 * CPU Auxiliary Control register specific definitions.
 ******************************************************************************/
-#define CORTEX_A53_ACTLR_EL1			S3_1_C15_C2_0
+#define CORTEX_A53_CPUACTLR_EL1				S3_1_C15_C2_0
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	U(44)
+#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT		U(44)
-#define CORTEX_A53_ACTLR_ENDCCASCI		(U(1) << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI		(U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
-#define CORTEX_A53_ACTLR_RADIS_SHIFT		U(27)
+#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT		U(27)
-#define CORTEX_A53_ACTLR_RADIS			(U(3) << CORTEX_A53_ACTLR_RADIS_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_RADIS			(U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
-#define CORTEX_A53_ACTLR_L1RADIS_SHIFT		U(25)
+#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT		U(25)
-#define CORTEX_A53_ACTLR_L1RADIS		(U(3) << CORTEX_A53_ACTLR_L1RADIS_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_L1RADIS			(U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
-#define CORTEX_A53_ACTLR_DTAH_SHIFT		U(24)
+#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT		U(24)
-#define CORTEX_A53_ACTLR_DTAH			(U(1) << CORTEX_A53_ACTLR_DTAH_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_DTAH			(U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
 /*******************************************************************************
 * L2 Auxiliary Control register specific definitions.
@@ -71,4 +71,21 @@
 ******************************************************************************/
 #define CORTEX_A53_L2MERRSR_EL1				S3_1_C15_C2_3
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions
+ * so as not to break platforms that continue using them.
+ */
+#define CORTEX_A53_ACTLR_EL1			CORTEX_A53_CPUACTLR_EL1
+#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT
+#define CORTEX_A53_ACTLR_ENDCCASCI		CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
+#define CORTEX_A53_ACTLR_RADIS_SHIFT		CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT
+#define CORTEX_A53_ACTLR_RADIS			CORTEX_A53_CPUACTLR_EL1_RADIS
+#define CORTEX_A53_ACTLR_L1RADIS_SHIFT		CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT
+#define CORTEX_A53_ACTLR_L1RADIS		CORTEX_A53_CPUACTLR_EL1_L1RADIS
+#define CORTEX_A53_ACTLR_DTAH_SHIFT		CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT
+#define CORTEX_A53_ACTLR_DTAH			CORTEX_A53_CPUACTLR_EL1_DTAH
+#endif /* !ERROR_DEPRECATED */
 #endif /* __CORTEX_A53_H__ */
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -41,17 +41,17 @@
 /*******************************************************************************
 * CPU Auxiliary Control register specific definitions.
 ******************************************************************************/
-#define CORTEX_A57_ACTLR_EL1			S3_1_C15_C2_0
+#define CORTEX_A57_CPUACTLR_EL1				S3_1_C15_C2_0
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	(ULL(1) << 59)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB	(ULL(1) << 59)
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	(ULL(1) << 54)
+#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE	(ULL(1) << 54)
-#define CORTEX_A57_ACTLR_DIS_OVERREAD		(ULL(1) << 52)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD		(ULL(1) << 52)
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
+#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA		(ULL(1) << 49)
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI		(ULL(1) << 44)
+#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI		(ULL(1) << 44)
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	(ULL(1) << 38)
+#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH	(ULL(1) << 38)
-#define CORTEX_A57_ACTLR_DIS_STREAMING		(ULL(3) << 27)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING		(ULL(3) << 27)
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	(ULL(3) << 25)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING	(ULL(3) << 25)
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	(ULL(1) << 4)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR	(ULL(1) << 4)
 /*******************************************************************************
 * L2 Control register specific definitions.
@@ -79,4 +79,22 @@
 ******************************************************************************/
 #define CORTEX_A57_L2MERRSR_EL1			S3_1_C15_C2_3
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A57_ACTLR_EL1			CORTEX_A57_CPUACTLR_EL1
+#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
+#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
+#define CORTEX_A57_ACTLR_DIS_OVERREAD		CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
+#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
+#define CORTEX_A57_ACTLR_DCC_AS_DCCI		CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
+#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
+#define CORTEX_A57_ACTLR_DIS_STREAMING		CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING
+#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING
+#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
+#endif /* !ERROR_DEPRECATED */
 #endif /* __CORTEX_A57_H__ */
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -29,11 +29,11 @@
 /*******************************************************************************
 * CPU Auxiliary Control register specific definitions.
 ******************************************************************************/
-#define CORTEX_A72_ACTLR_EL1				S3_1_C15_C2_0
+#define CORTEX_A72_CPUACTLR_EL1					S3_1_C15_C2_0
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
+#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			(ULL(1) << 49)
+#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA			(ULL(1) << 49)
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI			(ULL(1) << 44)
+#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI			(ULL(1) << 44)
 /*******************************************************************************
 * L2 Control register specific definitions.
@@ -52,4 +52,16 @@
 ******************************************************************************/
 #define CORTEX_A72_L2MERRSR_EL1				S3_1_C15_C2_3
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A72_ACTLR				CORTEX_A72_CPUACTLR_EL1
+#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
+#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
+#define CORTEX_A72_ACTLR_DCC_AS_DCCI			CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
+#endif /* !ERROR_DEPRECATED */
 #endif /* __CORTEX_A72_H__ */
--- a/lib/cpus/aarch32/cortex_a53.S
+++ b/lib/cpus/aarch32/cortex_a53.S
@@ -84,9 +84,9 @@ func a53_disable_non_temporal_hint
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A53_ACTLR
+	ldcopr16	r0, r1, CORTEX_A53_CPUACTLR
-	orr64_imm	r0, r1, CORTEX_A53_ACTLR_DTAH
+	orr64_imm	r0, r1, CORTEX_A53_CPUACTLR_DTAH
-	stcopr16	r0, r1, CORTEX_A53_ACTLR
+	stcopr16	r0, r1, CORTEX_A53_CPUACTLR
 1:
 	bx		lr
 endfunc a53_disable_non_temporal_hint
@@ -118,9 +118,9 @@ func errata_a53_855873_wa
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A53_ACTLR
+	ldcopr16	r0, r1, CORTEX_A53_CPUACTLR
-	orr64_imm	r0, r1, CORTEX_A53_ACTLR_ENDCCASCI
+	orr64_imm	r0, r1, CORTEX_A53_CPUACTLR_ENDCCASCI
-	stcopr16	r0, r1, CORTEX_A53_ACTLR
+	stcopr16	r0, r1, CORTEX_A53_CPUACTLR
 1:
 	bx		lr
 endfunc errata_a53_855873_wa

--- a/lib/cpus/aarch32/cortex_a57.S
+++ b/lib/cpus/aarch32/cortex_a57.S
@@ -67,9 +67,9 @@ func errata_a57_806969_wa
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A57_ACTLR
+	ldcopr16	r0, r1, CORTEX_A57_CPUACTLR
-	orr64_imm	r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
+	orr64_imm	r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
-	stcopr16	r0, r1, CORTEX_A57_ACTLR
+	stcopr16	r0, r1, CORTEX_A57_CPUACTLR
 1:
 	bx	lr
 endfunc errata_a57_806969_wa
@@ -111,9 +111,9 @@ func errata_a57_813420_wa
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A57_ACTLR
+	ldcopr16	r0, r1, CORTEX_A57_CPUACTLR
-	orr64_imm	r0, r1, CORTEX_A57_ACTLR_DCC_AS_DCCI
+	orr64_imm	r0, r1, CORTEX_A57_CPUACTLR_DCC_AS_DCCI
-	stcopr16	r0, r1, CORTEX_A57_ACTLR
+	stcopr16	r0, r1, CORTEX_A57_CPUACTLR
 1:
 	bx		lr
 endfunc errata_a57_813420_wa
@@ -143,9 +143,9 @@ func a57_disable_ldnp_overread
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A57_ACTLR
+	ldcopr16	r0, r1, CORTEX_A57_CPUACTLR
-	orr64_imm	r0, r1, CORTEX_A57_ACTLR_DIS_OVERREAD
+	orr64_imm	r0, r1, CORTEX_A57_CPUACTLR_DIS_OVERREAD
-	stcopr16	r0, r1, CORTEX_A57_ACTLR
+	stcopr16	r0, r1, CORTEX_A57_CPUACTLR
 1:
 	bx		lr
 endfunc a57_disable_ldnp_overread
@@ -172,9 +172,9 @@ func errata_a57_826974_wa
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A57_ACTLR
+	ldcopr16	r0, r1, CORTEX_A57_CPUACTLR
-	orr64_imm	r0, r1, CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
+	orr64_imm	r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
-	stcopr16	r0, r1, CORTEX_A57_ACTLR
+	stcopr16	r0, r1, CORTEX_A57_CPUACTLR
 1:
 	bx		lr
 endfunc errata_a57_826974_wa
@@ -201,9 +201,9 @@ func errata_a57_826977_wa
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A57_ACTLR
+	ldcopr16	r0, r1, CORTEX_A57_CPUACTLR
-	orr64_imm	r0, r1, CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
+	orr64_imm	r0, r1, CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
-	stcopr16	r0, r1, CORTEX_A57_ACTLR
+	stcopr16	r0, r1, CORTEX_A57_CPUACTLR
 1:
 	bx		lr
 endfunc errata_a57_826977_wa
@@ -230,15 +230,15 @@ func errata_a57_828024_wa
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A57_ACTLR
+	ldcopr16	r0, r1, CORTEX_A57_CPUACTLR
 	/*
-	 * Setting the relevant bits in CORTEX_A57_ACTLR has to be done in 2
+	 * Setting the relevant bits in CORTEX_A57_CPUACTLR has to be done in 2
 	 * instructions here because the resulting bitmask doesn't fit in a
 	 * 16-bit value so it cannot be encoded in a single instruction.
 	 */
-	orr64_imm	r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
+	orr64_imm	r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
-	orr64_imm	r0, r1, (CORTEX_A57_ACTLR_DIS_L1_STREAMING | CORTEX_A57_ACTLR_DIS_STREAMING)
+	orr64_imm	r0, r1, (CORTEX_A57_CPUACTLR_DIS_L1_STREAMING | CORTEX_A57_CPUACTLR_DIS_STREAMING)
-	stcopr16	r0, r1, CORTEX_A57_ACTLR
+	stcopr16	r0, r1, CORTEX_A57_CPUACTLR
 1:
 	bx		lr
 endfunc errata_a57_828024_wa
@@ -265,9 +265,9 @@ func errata_a57_829520_wa
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A57_ACTLR
+	ldcopr16	r0, r1, CORTEX_A57_CPUACTLR
-	orr64_imm	r0, r1, CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
+	orr64_imm	r0, r1, CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
-	stcopr16	r0, r1, CORTEX_A57_ACTLR
+	stcopr16	r0, r1, CORTEX_A57_CPUACTLR
 1:
 	bx		lr
 endfunc errata_a57_829520_wa
@@ -294,9 +294,9 @@ func errata_a57_833471_wa
 	mov		lr, r2
 	cmp		r0, #ERRATA_NOT_APPLIES
 	beq		1f
-	ldcopr16	r0, r1, CORTEX_A57_ACTLR
+	ldcopr16	r0, r1, CORTEX_A57_CPUACTLR
-	orr64_imm	r1, r1, CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
+	orr64_imm	r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
-	stcopr16	r0, r1, CORTEX_A57_ACTLR
+	stcopr16	r0, r1, CORTEX_A57_CPUACTLR
 1:
 	bx		lr
 endfunc errata_a57_833471_wa

--- a/lib/cpus/aarch32/cortex_a72.S
+++ b/lib/cpus/aarch32/cortex_a72.S
@@ -29,9 +29,9 @@ endfunc cortex_a72_disable_l2_prefetch
 	 * ---------------------------------------------
 	 */
 func cortex_a72_disable_hw_prefetcher
-	ldcopr16	r0, r1, CORTEX_A72_ACTLR
+	ldcopr16	r0, r1, CORTEX_A72_CPUACTLR
-	orr64_imm	r0, r1, CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
+	orr64_imm	r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
-	stcopr16	r0, r1, CORTEX_A72_ACTLR
+	stcopr16	r0, r1, CORTEX_A72_CPUACTLR
 	isb
 	dsb	ish
 	bx	lr

--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -93,9 +93,9 @@ func a53_disable_non_temporal_hint
 	mov	x17, x30
 	bl	check_errata_disable_non_temporal_hint
 	cbz	x0, 1f
-	mrs	x1, CORTEX_A53_ACTLR_EL1
+	mrs	x1, CORTEX_A53_CPUACTLR_EL1
-	orr	x1, x1, #CORTEX_A53_ACTLR_DTAH
+	orr	x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH
-	msr	CORTEX_A53_ACTLR_EL1, x1
+	msr	CORTEX_A53_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc a53_disable_non_temporal_hint
@@ -126,9 +126,9 @@ func errata_a53_855873_wa
        bl      check_errata_855873
        cbz     x0, 1f
-	mrs	x1, CORTEX_A53_ACTLR_EL1
+	mrs	x1, CORTEX_A53_CPUACTLR_EL1
-	orr	x1, x1, #CORTEX_A53_ACTLR_ENDCCASCI
+	orr	x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
-	msr	CORTEX_A53_ACTLR_EL1, x1
+	msr	CORTEX_A53_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc errata_a53_855873_wa
@@ -300,7 +300,7 @@ func cortex_a53_cpu_reg_dump
 	mrs	x8, CORTEX_A53_ECTLR_EL1
 	mrs	x9, CORTEX_A53_MERRSR_EL1
 	mrs	x10, CORTEX_A53_L2MERRSR_EL1
-	mrs	x11, CORTEX_A53_ACTLR_EL1
+	mrs	x11, CORTEX_A53_CPUACTLR_EL1
 	ret
 endfunc cortex_a53_cpu_reg_dump

--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -78,9 +78,9 @@ func errata_a57_806969_wa
 	mov	x17, x30
 	bl	check_errata_806969
 	cbz	x0, 1f
-	mrs	x1, CORTEX_A57_ACTLR_EL1
+	mrs	x1, CORTEX_A57_CPUACTLR_EL1
-	orr	x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
+	orr	x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
-	msr	CORTEX_A57_ACTLR_EL1, x1
+	msr	CORTEX_A57_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc errata_a57_806969_wa
@@ -120,9 +120,9 @@ func errata_a57_813420_wa
 	mov	x17, x30
 	bl	check_errata_813420
 	cbz	x0, 1f
-	mrs	x1, CORTEX_A57_ACTLR_EL1
+	mrs	x1, CORTEX_A57_CPUACTLR_EL1
-	orr	x1, x1, #CORTEX_A57_ACTLR_DCC_AS_DCCI
+	orr	x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
-	msr	CORTEX_A57_ACTLR_EL1, x1
+	msr	CORTEX_A57_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc errata_a57_813420_wa
@@ -150,9 +150,9 @@ func a57_disable_ldnp_overread
 	mov	x17, x30
 	bl	check_errata_disable_ldnp_overread
 	cbz	x0, 1f
-	mrs	x1, CORTEX_A57_ACTLR_EL1
+	mrs	x1, CORTEX_A57_CPUACTLR_EL1
-	orr	x1, x1, #CORTEX_A57_ACTLR_DIS_OVERREAD
+	orr	x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
-	msr	CORTEX_A57_ACTLR_EL1, x1
+	msr	CORTEX_A57_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc a57_disable_ldnp_overread
@@ -177,9 +177,9 @@ func errata_a57_826974_wa
 	mov	x17, x30
 	bl	check_errata_826974
 	cbz	x0, 1f
-	mrs	x1, CORTEX_A57_ACTLR_EL1
+	mrs	x1, CORTEX_A57_CPUACTLR_EL1
-	orr	x1, x1, #CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
+	orr	x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
-	msr	CORTEX_A57_ACTLR_EL1, x1
+	msr	CORTEX_A57_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc errata_a57_826974_wa
@@ -204,9 +204,9 @@ func errata_a57_826977_wa
 	mov	x17, x30
 	bl	check_errata_826977
 	cbz	x0, 1f
-	mrs	x1, CORTEX_A57_ACTLR_EL1
+	mrs	x1, CORTEX_A57_CPUACTLR_EL1
-	orr	x1, x1, #CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
+	orr	x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
-	msr	CORTEX_A57_ACTLR_EL1, x1
+	msr	CORTEX_A57_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc errata_a57_826977_wa
@@ -231,16 +231,16 @@ func errata_a57_828024_wa
 	mov	x17, x30
 	bl	check_errata_828024
 	cbz	x0, 1f
-	mrs	x1, CORTEX_A57_ACTLR_EL1
+	mrs	x1, CORTEX_A57_CPUACTLR_EL1
 	/*
 	 * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
 	 * instructions here because the resulting bitmask doesn't fit in a
 	 * 16-bit value so it cannot be encoded in a single instruction.
 	 */
-	orr	x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
+	orr	x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
-	orr	x1, x1, #(CORTEX_A57_ACTLR_DIS_L1_STREAMING | \
+	orr	x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \
-			  CORTEX_A57_ACTLR_DIS_STREAMING)
+			  CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING)
-	msr	CORTEX_A57_ACTLR_EL1, x1
+	msr	CORTEX_A57_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc errata_a57_828024_wa
@@ -265,9 +265,9 @@ func errata_a57_829520_wa
 	mov	x17, x30
 	bl	check_errata_829520
 	cbz	x0, 1f
-	mrs	x1, CORTEX_A57_ACTLR_EL1
+	mrs	x1, CORTEX_A57_CPUACTLR_EL1
-	orr	x1, x1, #CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
+	orr	x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
-	msr	CORTEX_A57_ACTLR_EL1, x1
+	msr	CORTEX_A57_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc errata_a57_829520_wa
@@ -292,9 +292,9 @@ func errata_a57_833471_wa
 	mov	x17, x30
 	bl	check_errata_833471
 	cbz	x0, 1f
-	mrs	x1, CORTEX_A57_ACTLR_EL1
+	mrs	x1, CORTEX_A57_CPUACTLR_EL1
-	orr	x1, x1, #CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
+	orr	x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
-	msr	CORTEX_A57_ACTLR_EL1, x1
+	msr	CORTEX_A57_CPUACTLR_EL1, x1
 1:
 	ret	x17
 endfunc errata_a57_833471_wa

--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@@ -42,9 +42,9 @@ endfunc cortex_a72_disable_l2_prefetch
 	 * ---------------------------------------------
 	 */
 func cortex_a72_disable_hw_prefetcher
-	mrs	x0, CORTEX_A72_ACTLR_EL1
+	mrs	x0, CORTEX_A72_CPUACTLR_EL1
-	orr	x0, x0, #CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
+	orr	x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
-	msr	CORTEX_A72_ACTLR_EL1, x0
+	msr	CORTEX_A72_CPUACTLR_EL1, x0
 	isb
 	dsb	ish
 	ret