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Unverified Commit 9a93d8cc authored by Dimitris Papastamos's avatar Dimitris Papastamos Committed by GitHub
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Merge pull request #1460 from robertovargas-arm/clang 

Make TF compatible with Clang assembler and linker
parents 89a79342 4a98f0ef
master v2.5 v2.5-rc1 v2.5-rc0 v2.4 v2.4-rc2 v2.4-rc1 v2.4-rc0 v2.3 v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.2 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.1 v2.1-rc1 v2.1-rc0 v2.0 v2.0-rc0 v1.6 v1.6-rc1 v1.6-rc0 arm_cca_v0.2 arm_cca_v0.1
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lib/cpus/aarch64/cortex_a76.S
View file @ 9a93d8cc
......@@ -107,19 +107,19 @@ vector_base cortex_a76_wa_cve_2018_3639_a76_vbar
*/
vector_entry cortex_a76_sync_exception_sp_el0
b sync_exception_sp_el0
check_vector_size cortex_a76_sync_exception_sp_el0
end_vector_entry cortex_a76_sync_exception_sp_el0
vector_entry cortex_a76_irq_sp_el0
b irq_sp_el0
check_vector_size cortex_a76_irq_sp_el0
end_vector_entry cortex_a76_irq_sp_el0
vector_entry cortex_a76_fiq_sp_el0
b fiq_sp_el0
check_vector_size cortex_a76_fiq_sp_el0
end_vector_entry cortex_a76_fiq_sp_el0
vector_entry cortex_a76_serror_sp_el0
b serror_sp_el0
check_vector_size cortex_a76_serror_sp_el0
end_vector_entry cortex_a76_serror_sp_el0
/* ---------------------------------------------------------------------
* Current EL with SP_ELx: 0x200 - 0x400
......@@ -127,19 +127,19 @@ vector_entry cortex_a76_serror_sp_el0
*/
vector_entry cortex_a76_sync_exception_sp_elx
b sync_exception_sp_elx
check_vector_size cortex_a76_sync_exception_sp_elx
end_vector_entry cortex_a76_sync_exception_sp_elx
vector_entry cortex_a76_irq_sp_elx
b irq_sp_elx
check_vector_size cortex_a76_irq_sp_elx
end_vector_entry cortex_a76_irq_sp_elx
vector_entry cortex_a76_fiq_sp_elx
b fiq_sp_elx
check_vector_size cortex_a76_fiq_sp_elx
end_vector_entry cortex_a76_fiq_sp_elx
vector_entry cortex_a76_serror_sp_elx
b serror_sp_elx
check_vector_size cortex_a76_serror_sp_elx
end_vector_entry cortex_a76_serror_sp_elx
/* ---------------------------------------------------------------------
* Lower EL using AArch64 : 0x400 - 0x600
......@@ -148,22 +148,22 @@ vector_entry cortex_a76_serror_sp_elx
vector_entry cortex_a76_sync_exception_aarch64
apply_cve_2018_3639_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A64_SMC0
b sync_exception_aarch64
check_vector_size cortex_a76_sync_exception_aarch64
end_vector_entry cortex_a76_sync_exception_aarch64
vector_entry cortex_a76_irq_aarch64
apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
b irq_aarch64
check_vector_size cortex_a76_irq_aarch64
end_vector_entry cortex_a76_irq_aarch64
vector_entry cortex_a76_fiq_aarch64
apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
b fiq_aarch64
check_vector_size cortex_a76_fiq_aarch64
end_vector_entry cortex_a76_fiq_aarch64
vector_entry cortex_a76_serror_aarch64
apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
b serror_aarch64
check_vector_size cortex_a76_serror_aarch64
end_vector_entry cortex_a76_serror_aarch64
/* ---------------------------------------------------------------------
* Lower EL using AArch32 : 0x600 - 0x800
......@@ -172,22 +172,22 @@ vector_entry cortex_a76_serror_aarch64
vector_entry cortex_a76_sync_exception_aarch32
apply_cve_2018_3639_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A32_SMC0
b sync_exception_aarch32
check_vector_size cortex_a76_sync_exception_aarch32
end_vector_entry cortex_a76_sync_exception_aarch32
vector_entry cortex_a76_irq_aarch32
apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
b irq_aarch32
check_vector_size cortex_a76_irq_aarch32
end_vector_entry cortex_a76_irq_aarch32
vector_entry cortex_a76_fiq_aarch32
apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
b fiq_aarch32
check_vector_size cortex_a76_fiq_aarch32
end_vector_entry cortex_a76_fiq_aarch32
vector_entry cortex_a76_serror_aarch32
apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
b serror_aarch32
check_vector_size cortex_a76_serror_aarch32
end_vector_entry cortex_a76_serror_aarch32
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
......
lib/cpus/aarch64/denver.S
View file @ 9a93d8cc
......@@ -55,19 +55,19 @@ vector_base workaround_bpflush_runtime_exceptions
*/
vector_entry workaround_bpflush_sync_exception_sp_el0
b sync_exception_sp_el0
check_vector_size workaround_bpflush_sync_exception_sp_el0
end_vector_entry workaround_bpflush_sync_exception_sp_el0
vector_entry workaround_bpflush_irq_sp_el0
b irq_sp_el0
check_vector_size workaround_bpflush_irq_sp_el0
end_vector_entry workaround_bpflush_irq_sp_el0
vector_entry workaround_bpflush_fiq_sp_el0
b fiq_sp_el0
check_vector_size workaround_bpflush_fiq_sp_el0
end_vector_entry workaround_bpflush_fiq_sp_el0
vector_entry workaround_bpflush_serror_sp_el0
b serror_sp_el0
check_vector_size workaround_bpflush_serror_sp_el0
end_vector_entry workaround_bpflush_serror_sp_el0
/* ---------------------------------------------------------------------
* Current EL with SP_ELx: 0x200 - 0x400
......@@ -75,19 +75,19 @@ vector_entry workaround_bpflush_serror_sp_el0
*/
vector_entry workaround_bpflush_sync_exception_sp_elx
b sync_exception_sp_elx
check_vector_size workaround_bpflush_sync_exception_sp_elx
end_vector_entry workaround_bpflush_sync_exception_sp_elx
vector_entry workaround_bpflush_irq_sp_elx
b irq_sp_elx
check_vector_size workaround_bpflush_irq_sp_elx
end_vector_entry workaround_bpflush_irq_sp_elx
vector_entry workaround_bpflush_fiq_sp_elx
b fiq_sp_elx
check_vector_size workaround_bpflush_fiq_sp_elx
end_vector_entry workaround_bpflush_fiq_sp_elx
vector_entry workaround_bpflush_serror_sp_elx
b serror_sp_elx
check_vector_size workaround_bpflush_serror_sp_elx
end_vector_entry workaround_bpflush_serror_sp_elx
/* ---------------------------------------------------------------------
* Lower EL using AArch64 : 0x400 - 0x600
......@@ -96,22 +96,22 @@ vector_entry workaround_bpflush_serror_sp_elx
vector_entry workaround_bpflush_sync_exception_aarch64
apply_workaround
b sync_exception_aarch64
check_vector_size workaround_bpflush_sync_exception_aarch64
end_vector_entry workaround_bpflush_sync_exception_aarch64
vector_entry workaround_bpflush_irq_aarch64
apply_workaround
b irq_aarch64
check_vector_size workaround_bpflush_irq_aarch64
end_vector_entry workaround_bpflush_irq_aarch64
vector_entry workaround_bpflush_fiq_aarch64
apply_workaround
b fiq_aarch64
check_vector_size workaround_bpflush_fiq_aarch64
end_vector_entry workaround_bpflush_fiq_aarch64
vector_entry workaround_bpflush_serror_aarch64
apply_workaround
b serror_aarch64
check_vector_size workaround_bpflush_serror_aarch64
end_vector_entry workaround_bpflush_serror_aarch64
/* ---------------------------------------------------------------------
* Lower EL using AArch32 : 0x600 - 0x800
......@@ -120,22 +120,22 @@ vector_entry workaround_bpflush_serror_aarch64
vector_entry workaround_bpflush_sync_exception_aarch32
apply_workaround
b sync_exception_aarch32
check_vector_size workaround_bpflush_sync_exception_aarch32
end_vector_entry workaround_bpflush_sync_exception_aarch32
vector_entry workaround_bpflush_irq_aarch32
apply_workaround
b irq_aarch32
check_vector_size workaround_bpflush_irq_aarch32
end_vector_entry workaround_bpflush_irq_aarch32
vector_entry workaround_bpflush_fiq_aarch32
apply_workaround
b fiq_aarch32
check_vector_size workaround_bpflush_fiq_aarch32
end_vector_entry workaround_bpflush_fiq_aarch32
vector_entry workaround_bpflush_serror_aarch32
apply_workaround
b serror_aarch32
check_vector_size workaround_bpflush_serror_aarch32
end_vector_entry workaround_bpflush_serror_aarch32
.global denver_disable_dco
......
lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
View file @ 9a93d8cc
......@@ -114,19 +114,19 @@ aarch32_stub:
.word EMIT_BPIALL
.word EMIT_SMC
check_vector_size bpiall_sync_exception_sp_el0
end_vector_entry bpiall_sync_exception_sp_el0
vector_entry bpiall_irq_sp_el0
b irq_sp_el0
check_vector_size bpiall_irq_sp_el0
end_vector_entry bpiall_irq_sp_el0
vector_entry bpiall_fiq_sp_el0
b fiq_sp_el0
check_vector_size bpiall_fiq_sp_el0
end_vector_entry bpiall_fiq_sp_el0
vector_entry bpiall_serror_sp_el0
b serror_sp_el0
check_vector_size bpiall_serror_sp_el0
end_vector_entry bpiall_serror_sp_el0
/* ---------------------------------------------------------------------
* Current EL with SP_ELx: 0x200 - 0x400
......@@ -134,19 +134,19 @@ vector_entry bpiall_serror_sp_el0
*/
vector_entry bpiall_sync_exception_sp_elx
b sync_exception_sp_elx
check_vector_size bpiall_sync_exception_sp_elx
end_vector_entry bpiall_sync_exception_sp_elx
vector_entry bpiall_irq_sp_elx
b irq_sp_elx
check_vector_size bpiall_irq_sp_elx
end_vector_entry bpiall_irq_sp_elx
vector_entry bpiall_fiq_sp_elx
b fiq_sp_elx
check_vector_size bpiall_fiq_sp_elx
end_vector_entry bpiall_fiq_sp_elx
vector_entry bpiall_serror_sp_elx
b serror_sp_elx
check_vector_size bpiall_serror_sp_elx
end_vector_entry bpiall_serror_sp_elx
/* ---------------------------------------------------------------------
* Lower EL using AArch64 : 0x400 - 0x600
......@@ -154,19 +154,19 @@ vector_entry bpiall_serror_sp_elx
*/
vector_entry bpiall_sync_exception_aarch64
apply_cve_2017_5715_wa 1
check_vector_size bpiall_sync_exception_aarch64
end_vector_entry bpiall_sync_exception_aarch64
vector_entry bpiall_irq_aarch64
apply_cve_2017_5715_wa 2
check_vector_size bpiall_irq_aarch64
end_vector_entry bpiall_irq_aarch64
vector_entry bpiall_fiq_aarch64
apply_cve_2017_5715_wa 4
check_vector_size bpiall_fiq_aarch64
end_vector_entry bpiall_fiq_aarch64
vector_entry bpiall_serror_aarch64
apply_cve_2017_5715_wa 8
check_vector_size bpiall_serror_aarch64
end_vector_entry bpiall_serror_aarch64
/* ---------------------------------------------------------------------
* Lower EL using AArch32 : 0x600 - 0x800
......@@ -174,19 +174,19 @@ vector_entry bpiall_serror_aarch64
*/
vector_entry bpiall_sync_exception_aarch32
apply_cve_2017_5715_wa 1
check_vector_size bpiall_sync_exception_aarch32
end_vector_entry bpiall_sync_exception_aarch32
vector_entry bpiall_irq_aarch32
apply_cve_2017_5715_wa 2
check_vector_size bpiall_irq_aarch32
end_vector_entry bpiall_irq_aarch32
vector_entry bpiall_fiq_aarch32
apply_cve_2017_5715_wa 4
check_vector_size bpiall_fiq_aarch32
end_vector_entry bpiall_fiq_aarch32
vector_entry bpiall_serror_aarch32
apply_cve_2017_5715_wa 8
check_vector_size bpiall_serror_aarch32
end_vector_entry bpiall_serror_aarch32
/* ---------------------------------------------------------------------
* This vector table is used while the workaround is executing. It
......@@ -203,19 +203,19 @@ vector_base wa_cve_2017_5715_bpiall_ret_vbar
*/
vector_entry bpiall_ret_sync_exception_sp_el0
b report_unhandled_exception
check_vector_size bpiall_ret_sync_exception_sp_el0
end_vector_entry bpiall_ret_sync_exception_sp_el0
vector_entry bpiall_ret_irq_sp_el0
b report_unhandled_interrupt
check_vector_size bpiall_ret_irq_sp_el0
end_vector_entry bpiall_ret_irq_sp_el0
vector_entry bpiall_ret_fiq_sp_el0
b report_unhandled_interrupt
check_vector_size bpiall_ret_fiq_sp_el0
end_vector_entry bpiall_ret_fiq_sp_el0
vector_entry bpiall_ret_serror_sp_el0
b report_unhandled_exception
check_vector_size bpiall_ret_serror_sp_el0
end_vector_entry bpiall_ret_serror_sp_el0
/* ---------------------------------------------------------------------
* Current EL with SP_ELx: 0x200 - 0x400 (UNUSED)
......@@ -223,19 +223,19 @@ vector_entry bpiall_ret_serror_sp_el0
*/
vector_entry bpiall_ret_sync_exception_sp_elx
b report_unhandled_exception
check_vector_size bpiall_ret_sync_exception_sp_elx
end_vector_entry bpiall_ret_sync_exception_sp_elx
vector_entry bpiall_ret_irq_sp_elx
b report_unhandled_interrupt
check_vector_size bpiall_ret_irq_sp_elx
end_vector_entry bpiall_ret_irq_sp_elx
vector_entry bpiall_ret_fiq_sp_elx
b report_unhandled_interrupt
check_vector_size bpiall_ret_fiq_sp_elx
end_vector_entry bpiall_ret_fiq_sp_elx
vector_entry bpiall_ret_serror_sp_elx
b report_unhandled_exception
check_vector_size bpiall_ret_serror_sp_elx
end_vector_entry bpiall_ret_serror_sp_elx
/* ---------------------------------------------------------------------
* Lower EL using AArch64 : 0x400 - 0x600 (UNUSED)
......@@ -243,19 +243,19 @@ vector_entry bpiall_ret_serror_sp_elx
*/
vector_entry bpiall_ret_sync_exception_aarch64
b report_unhandled_exception
check_vector_size bpiall_ret_sync_exception_aarch64
end_vector_entry bpiall_ret_sync_exception_aarch64
vector_entry bpiall_ret_irq_aarch64
b report_unhandled_interrupt
check_vector_size bpiall_ret_irq_aarch64
end_vector_entry bpiall_ret_irq_aarch64
vector_entry bpiall_ret_fiq_aarch64
b report_unhandled_interrupt
check_vector_size bpiall_ret_fiq_aarch64
end_vector_entry bpiall_ret_fiq_aarch64
vector_entry bpiall_ret_serror_aarch64
b report_unhandled_exception
check_vector_size bpiall_ret_serror_aarch64
end_vector_entry bpiall_ret_serror_aarch64
/* ---------------------------------------------------------------------
* Lower EL using AArch32 : 0x600 - 0x800
......@@ -324,7 +324,7 @@ vector_entry bpiall_ret_sync_exception_aarch32
1:
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
b sync_exception_aarch64
check_vector_size bpiall_ret_sync_exception_aarch32
end_vector_entry bpiall_ret_sync_exception_aarch32
vector_entry bpiall_ret_irq_aarch32
b report_unhandled_interrupt
......@@ -346,12 +346,12 @@ bpiall_ret_fiq:
bpiall_ret_serror:
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
b serror_aarch64
check_vector_size bpiall_ret_irq_aarch32
end_vector_entry bpiall_ret_irq_aarch32
vector_entry bpiall_ret_fiq_aarch32
b report_unhandled_interrupt
check_vector_size bpiall_ret_fiq_aarch32
end_vector_entry bpiall_ret_fiq_aarch32
vector_entry bpiall_ret_serror_aarch32
b report_unhandled_exception
check_vector_size bpiall_ret_serror_aarch32
end_vector_entry bpiall_ret_serror_aarch32
lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
View file @ 9a93d8cc
......@@ -66,19 +66,19 @@ vector_base wa_cve_2017_5715_mmu_vbar
*/
vector_entry mmu_sync_exception_sp_el0
b sync_exception_sp_el0
check_vector_size mmu_sync_exception_sp_el0
end_vector_entry mmu_sync_exception_sp_el0
vector_entry mmu_irq_sp_el0
b irq_sp_el0
check_vector_size mmu_irq_sp_el0
end_vector_entry mmu_irq_sp_el0
vector_entry mmu_fiq_sp_el0
b fiq_sp_el0
check_vector_size mmu_fiq_sp_el0
end_vector_entry mmu_fiq_sp_el0
vector_entry mmu_serror_sp_el0
b serror_sp_el0
check_vector_size mmu_serror_sp_el0
end_vector_entry mmu_serror_sp_el0
/* ---------------------------------------------------------------------
* Current EL with SP_ELx: 0x200 - 0x400
......@@ -86,19 +86,19 @@ vector_entry mmu_serror_sp_el0
*/
vector_entry mmu_sync_exception_sp_elx
b sync_exception_sp_elx
check_vector_size mmu_sync_exception_sp_elx
end_vector_entry mmu_sync_exception_sp_elx
vector_entry mmu_irq_sp_elx
b irq_sp_elx
check_vector_size mmu_irq_sp_elx
end_vector_entry mmu_irq_sp_elx
vector_entry mmu_fiq_sp_elx
b fiq_sp_elx
check_vector_size mmu_fiq_sp_elx
end_vector_entry mmu_fiq_sp_elx
vector_entry mmu_serror_sp_elx
b serror_sp_elx
check_vector_size mmu_serror_sp_elx
end_vector_entry mmu_serror_sp_elx
/* ---------------------------------------------------------------------
* Lower EL using AArch64 : 0x400 - 0x600
......@@ -107,22 +107,22 @@ vector_entry mmu_serror_sp_elx
vector_entry mmu_sync_exception_aarch64
apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A64_SMC0
b sync_exception_aarch64
check_vector_size mmu_sync_exception_aarch64
end_vector_entry mmu_sync_exception_aarch64
vector_entry mmu_irq_aarch64
apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
b irq_aarch64
check_vector_size mmu_irq_aarch64
end_vector_entry mmu_irq_aarch64
vector_entry mmu_fiq_aarch64
apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
b fiq_aarch64
check_vector_size mmu_fiq_aarch64
end_vector_entry mmu_fiq_aarch64
vector_entry mmu_serror_aarch64
apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
b serror_aarch64
check_vector_size mmu_serror_aarch64
end_vector_entry mmu_serror_aarch64
/* ---------------------------------------------------------------------
* Lower EL using AArch32 : 0x600 - 0x800
......@@ -131,19 +131,19 @@ vector_entry mmu_serror_aarch64
vector_entry mmu_sync_exception_aarch32
apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A32_SMC0
b sync_exception_aarch32
check_vector_size mmu_sync_exception_aarch32
end_vector_entry mmu_sync_exception_aarch32
vector_entry mmu_irq_aarch32
apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
b irq_aarch32
check_vector_size mmu_irq_aarch32
end_vector_entry mmu_irq_aarch32
vector_entry mmu_fiq_aarch32
apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
b fiq_aarch32
check_vector_size mmu_fiq_aarch32
end_vector_entry mmu_fiq_aarch32
vector_entry mmu_serror_aarch32
apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
b serror_aarch32
check_vector_size mmu_serror_aarch32
end_vector_entry mmu_serror_aarch32
plat/mediatek/mt6795/bl31.ld.S
View file @ 9a93d8cc
......@@ -59,7 +59,7 @@ SECTIONS
* executable. No RW data from the next section must creep in.
* Ensure the rest of the current memory page is unused.
*/
. = NEXT(PAGE_SIZE);
. = ALIGN(PAGE_SIZE);
__RO_END__ = .;
} >RAM
......@@ -161,7 +161,7 @@ SECTIONS
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
. = NEXT(PAGE_SIZE);
. = ALIGN(PAGE_SIZE);
__COHERENT_RAM_END__ = .;
} >RAM2
#endif
......
plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
View file @ 9a93d8cc
......@@ -12,7 +12,6 @@
.macro pmusram_entry_func _name
.section .pmusram.entry, "ax"
.type \_name, %function
.func \_name
.cfi_startproc
\_name:
.endm
......
plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S
View file @ 9a93d8cc
......@@ -15,7 +15,6 @@
.cfi_sections .debug_frame
.section .sram.text, "ax"
.type \_name, %function
.func \_name
.cfi_startproc
\_name:
.endm
......
services/std_svc/spm/aarch64/spm_shim_exceptions.S
View file @ 9a93d8cc
......@@ -23,19 +23,19 @@ vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions
*/
vector_entry SynchronousExceptionSP0, .spm_shim_exceptions
b .
check_vector_size SynchronousExceptionSP0
end_vector_entry SynchronousExceptionSP0
vector_entry IrqSP0, .spm_shim_exceptions
b .
check_vector_size IrqSP0
end_vector_entry IrqSP0
vector_entry FiqSP0, .spm_shim_exceptions
b .
check_vector_size FiqSP0
end_vector_entry FiqSP0
vector_entry SErrorSP0, .spm_shim_exceptions
b .
check_vector_size SErrorSP0
end_vector_entry SErrorSP0
/* -----------------------------------------------------
* Current EL with SPx: 0x200 - 0x400
......@@ -43,19 +43,19 @@ vector_entry SErrorSP0, .spm_shim_exceptions
*/
vector_entry SynchronousExceptionSPx, .spm_shim_exceptions
b .
check_vector_size SynchronousExceptionSPx
end_vector_entry SynchronousExceptionSPx
vector_entry IrqSPx, .spm_shim_exceptions
b .
check_vector_size IrqSPx
end_vector_entry IrqSPx
vector_entry FiqSPx, .spm_shim_exceptions
b .
check_vector_size FiqSPx
end_vector_entry FiqSPx
vector_entry SErrorSPx, .spm_shim_exceptions
b .
check_vector_size SErrorSPx
end_vector_entry SErrorSPx
/* -----------------------------------------------------
* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
......@@ -93,19 +93,19 @@ do_smc:
handle_sys_trap:
panic:
b panic
check_vector_size SynchronousExceptionA64
end_vector_entry SynchronousExceptionA64
vector_entry IrqA64, .spm_shim_exceptions
b .
check_vector_size IrqA64
end_vector_entry IrqA64
vector_entry FiqA64, .spm_shim_exceptions
b .
check_vector_size FiqA64
end_vector_entry FiqA64
vector_entry SErrorA64, .spm_shim_exceptions
b .
check_vector_size SErrorA64
end_vector_entry SErrorA64
/* -----------------------------------------------------
* Lower EL using AArch32 : 0x600 - 0x800
......@@ -113,16 +113,16 @@ vector_entry SErrorA64, .spm_shim_exceptions
*/
vector_entry SynchronousExceptionA32, .spm_shim_exceptions
b .
check_vector_size SynchronousExceptionA32
end_vector_entry SynchronousExceptionA32
vector_entry IrqA32, .spm_shim_exceptions
b .
check_vector_size IrqA32
end_vector_entry IrqA32
vector_entry FiqA32, .spm_shim_exceptions
b .
check_vector_size FiqA32
end_vector_entry FiqA32
vector_entry SErrorA32, .spm_shim_exceptions
b .
check_vector_size SErrorA32
end_vector_entry SErrorA32
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