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adam.huang
Arm Trusted Firmware
Commits
a6388e49
Unverified
Commit
a6388e49
authored
Mar 01, 2019
by
Antonio Niño Díaz
Committed by
GitHub
Mar 01, 2019
Browse files
Merge pull request #1815 from Anson-Huang/gic
gic: make sure ProcessorSleep bit clear successfully
parents
a4acc7f1
e655fefc
Changes
1
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plat/imx/common/plat_imx8_gic.c
View file @
a6388e49
...
@@ -9,6 +9,8 @@
...
@@ -9,6 +9,8 @@
#include <common/bl_common.h>
#include <common/bl_common.h>
#include <common/interrupt_props.h>
#include <common/interrupt_props.h>
#include <drivers/arm/gicv3.h>
#include <drivers/arm/gicv3.h>
#include <drivers/arm/arm_gicv3_common.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <plat/common/platform.h>
...
@@ -52,8 +54,27 @@ void plat_gic_driver_init(void)
...
@@ -52,8 +54,27 @@ void plat_gic_driver_init(void)
#endif
#endif
}
}
static
__inline
void
plat_gicr_exit_sleep
(
void
)
{
unsigned
int
val
=
mmio_read_32
(
PLAT_GICR_BASE
+
GICR_WAKER
);
/*
* ProcessorSleep bit can ONLY be set to zero when
* Quiescent bit and Sleep bit are both zero, so
* need to make sure Quiescent bit and Sleep bit
* are zero before clearing ProcessorSleep bit.
*/
if
(
val
&
WAKER_QSC_BIT
)
{
mmio_write_32
(
PLAT_GICR_BASE
+
GICR_WAKER
,
val
&
~
WAKER_SL_BIT
);
/* Wait till the WAKER_QSC_BIT changes to 0 */
while
((
mmio_read_32
(
PLAT_GICR_BASE
+
GICR_WAKER
)
&
WAKER_QSC_BIT
)
!=
0U
)
;
}
}
void
plat_gic_init
(
void
)
void
plat_gic_init
(
void
)
{
{
plat_gicr_exit_sleep
();
gicv3_distif_init
();
gicv3_distif_init
();
gicv3_rdistif_init
(
plat_my_core_pos
());
gicv3_rdistif_init
(
plat_my_core_pos
());
gicv3_cpuif_enable
(
plat_my_core_pos
());
gicv3_cpuif_enable
(
plat_my_core_pos
());
...
...
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