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Unverified Commit af4aad2f authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
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Merge pull request #1733 from vwadekar/tf2.0-tegra-downstream-rebase-1.3.19 

Tegra downstream rebase 1.3.19
parents cd1f39b4 0f426f8f
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docs/plat/nvidia-tegra.rst
View file @ af4aad2f
......@@ -80,6 +80,8 @@ uint64\_t tzdram\_size;
uint64\_t tzdram\_base;
/* UART port ID \*/
int uart\_id;
/* L2 ECC parity protection disable flag \*/
int l2\_ecc\_parity\_prot\_dis;
} plat\_params\_from\_bl2\_t;
Power Management
......
plat/nvidia/tegra/common/aarch64/tegra_helpers.S
View file @ af4aad2f
......@@ -11,6 +11,7 @@
#include <cortex_a57.h>
#include <platform_def.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#define MIDR_PN_CORTEX_A57 0xD07
......@@ -45,7 +46,6 @@
.globl ns_image_entrypoint
.globl tegra_bl31_phys_base
.globl tegra_console_base
.globl tegra_enable_l2_ecc_parity_prot
/* ---------------------
* Common CPU init code
......@@ -92,20 +92,6 @@
msr actlr_el2, x0
isb
/* -------------------------------------------------------
* Enable L2 ECC and Parity Protection
* -------------------------------------------------------
*/
adr x0, tegra_enable_l2_ecc_parity_prot
ldr x0, [x0]
cbz x0, 1f
mrs x0, CORTEX_A57_L2CTLR_EL1
and x1, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT
cbnz x1, 1f
orr x0, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT
msr CORTEX_A57_L2CTLR_EL1, x0
isb
/* --------------------------------
* Enable the cycle count register
* --------------------------------
......@@ -326,6 +312,23 @@ func tegra_secure_entrypoint _align=6
#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT
/* --------------------------------------------------------
* Skip the invalidate BTB workaround for Tegra210B01 SKUs.
* --------------------------------------------------------
*/
mov x0, #TEGRA_MISC_BASE
add x0, x0, #HARDWARE_REVISION_OFFSET
ldr w1, [x0]
lsr w1, w1, #CHIP_ID_SHIFT
and w1, w1, #CHIP_ID_MASK
cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */
b.ne 2f
ldr w1, [x0]
lsr w1, w1, #MAJOR_VERSION_SHIFT
and w1, w1, #MAJOR_VERSION_MASK
cmp w1, #0x02 /* T210 B01? */
b.eq 2f
/* -------------------------------------------------------
* Invalidate BTB along with I$ to remove any stale
* entries from the branch predictor array.
......@@ -382,7 +385,7 @@ func tegra_secure_entrypoint _align=6
.rept 65
nop
.endr
2:
/* --------------------------------------------------
* Do not insert instructions here
* --------------------------------------------------
......@@ -460,10 +463,3 @@ tegra_bl31_phys_base:
*/
tegra_console_base:
.quad 0
/* --------------------------------------------------
* Enable L2 ECC and Parity Protection
* --------------------------------------------------
*/
tegra_enable_l2_ecc_parity_prot:
.quad 0
plat/nvidia/tegra/common/drivers/bpmp/bpmp.c 0 → 100644
View file @ af4aad2f
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <assert.h>
#include <bpmp.h>
#include <common/debug.h>
#include <delay_timer.h>
#include <errno.h>
#include <mmio.h>
#include <platform.h>
#include <stdbool.h>
#include <string.h>
#include <tegra_def.h>
#define BPMP_TIMEOUT_10US 10
static uint32_t channel_base[NR_CHANNELS];
static uint32_t bpmp_init_state = BPMP_INIT_PENDING;
static uint32_t channel_field(unsigned int ch)
{
return mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET) & CH_MASK(ch);
}
static bool master_free(unsigned int ch)
{
return channel_field(ch) == MA_FREE(ch);
}
static bool master_acked(unsigned int ch)
{
return channel_field(ch) == MA_ACKD(ch);
}
static void signal_slave(unsigned int ch)
{
mmio_write_32(TEGRA_RES_SEMA_BASE + CLR_OFFSET, CH_MASK(ch));
}
static void free_master(unsigned int ch)
{
mmio_write_32(TEGRA_RES_SEMA_BASE + CLR_OFFSET,
MA_ACKD(ch) ^ MA_FREE(ch));
}
/* should be called with local irqs disabled */
int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
void *ib_data, int ib_sz)
{
unsigned int ch = (unsigned int)plat_my_core_pos();
mb_data_t *p = (mb_data_t *)(uintptr_t)channel_base[ch];
int32_t ret = -ETIMEDOUT, timeout = 0;
if (bpmp_init_state == BPMP_INIT_COMPLETE) {
/* loop until BPMP is free */
for (timeout = 0; timeout < BPMP_TIMEOUT_10US; timeout++) {
if (master_free(ch) == true) {
break;
}
udelay(1);
}
if (timeout != BPMP_TIMEOUT_10US) {
/* generate the command struct */
p->code = mrq;
p->flags = DO_ACK;
(void)memcpy((void *)p->data, ob_data, (size_t)ob_sz);
/* signal command ready to the BPMP */
signal_slave(ch);
mmio_write_32(TEGRA_PRI_ICTLR_BASE + CPU_IEP_FIR_SET,
(1UL << INT_SHR_SEM_OUTBOX_FULL));
/* loop until the command is executed */
for (timeout = 0; timeout < BPMP_TIMEOUT_10US; timeout++) {
if (master_acked(ch) == true) {
break;
}
udelay(1);
}
if (timeout != BPMP_TIMEOUT_10US) {
/* get the command response */
(void)memcpy(ib_data, (const void *)p->data,
(size_t)ib_sz);
/* return error code */
ret = p->code;
/* free this channel */
free_master(ch);
}
}
} else {
/* return error code */
ret = -EINVAL;
}
if (timeout == BPMP_TIMEOUT_10US) {
ERROR("Timed out waiting for bpmp's response");
}
return ret;
}
int tegra_bpmp_init(void)
{
uint32_t val, base;
unsigned int ch;
int ret = 0;
if (bpmp_init_state != BPMP_INIT_COMPLETE) {
/* check if the bpmp processor is alive. */
val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
if (val != SIGN_OF_LIFE) {
ERROR("BPMP precessor not available\n");
ret = -ENOTSUP;
}
/* check if clock for the atomics block is enabled */
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_ENB_V);
if ((val & CAR_ENABLE_ATOMICS) == 0) {
ERROR("Clock to the atomics block is disabled\n");
}
/* check if the atomics block is out of reset */
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_CLR_V);
if ((val & CAR_ENABLE_ATOMICS) == CAR_ENABLE_ATOMICS) {
ERROR("Reset to the atomics block is asserted\n");
}
/* base address to get the result from Atomics */
base = TEGRA_ATOMICS_BASE + RESULT0_REG_OFFSET;
/* channel area is setup by BPMP before signaling handshake */
for (ch = 0; ch < NR_CHANNELS; ch++) {
/* issue command to get the channel base address */
mmio_write_32(base, (ch << TRIGGER_ID_SHIFT) |
ATOMIC_CMD_GET);
/* get the base address for the channel */
channel_base[ch] = mmio_read_32(base);
/* increment result register offset */
base += 4UL;
}
/* mark state as "initialized" */
if (ret == 0)
bpmp_init_state = BPMP_INIT_COMPLETE;
/* the channel values have to be visible across all cpus */
flush_dcache_range((uint64_t)channel_base, sizeof(channel_base));
flush_dcache_range((uint64_t)&bpmp_init_state,
sizeof(bpmp_init_state));
INFO("%s: done\n", __func__);
}
return ret;
}
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
View file @ af4aad2f
......@@ -87,6 +87,9 @@ static void tegra_memctrl_reconfig_mss_clients(void)
* strongly ordered MSS clients. ROC needs to be single point
* of control on overriding the memory type. So, remove TSA's
* memtype override.
*
* MC clients with default SO_DEV override still enabled at TSA:
* AONW, BPMPW, SCEW, APEW
*/
#if ENABLE_AFI_DEVICE
mc_set_tsa_passthrough(AFIW);
......@@ -106,63 +109,121 @@ static void tegra_memctrl_reconfig_mss_clients(void)
mc_set_tsa_passthrough(AONDMAW);
mc_set_tsa_passthrough(SCEDMAW);
/*
* Change COH_PATH_OVERRIDE_SO_DEV from NO_OVERRIDE -> FORCE_COHERENT
* for boot and strongly ordered MSS clients. This steers all sodev
* transactions to ROC.
/* Parker has no IO Coherency support and need the following:
* Ordered MC Clients on Parker are AFI, EQOS, SATA, XUSB.
* ISO clients(DISP, VI, EQOS) should never snoop caches and
* don't need ROC/PCFIFO ordering.
* ISO clients(EQOS) that need ordering should use PCFIFO ordering
* and bypass ROC ordering by using FORCE_NON_COHERENT path.
* FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
* over SMMU attributes.
* Force all Normal memory transactions from ISO and non-ISO to be
* non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
* Force the SO_DEV transactions from ordered ISO clients(EQOS) to
* non-coherent path and enable MC PCFIFO interlock for ordering.
* Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
* XUSB, SATA) to coherent so that the transactions are
* ordered by ROC.
* PCFIFO ensure write ordering.
* Read after Write ordering is maintained/enforced by MC clients.
* Clients that need PCIe type write ordering must
* go through ROC ordering.
* Ordering enable for Read clients is not necessary.
* R5's and A9 would get necessary ordering from AXI and
* don't need ROC ordering enable:
* - MMIO ordering is through dev mapping and MMIO
* accesses bypass SMMU.
* - Normal memory is accessed through SMMU and ordering is
* ensured by client and AXI.
* - Ack point for Normal memory is WCAM in MC.
* - MMIO's can be early acked and AXI ensures dev memory ordering,
* Client ensures read/write direction change ordering.
* - See Bug 200312466 for more details.
*
* Change AXID_OVERRIDE/AXID_OVERRIDE_SO_DEV only for some clients
* whose AXI IDs we know and trust.
* CGID_TAG_ADR is only present from T186 A02. As this code is common
* between A01 and A02, tegra_memctrl_set_overrides() programs
* CGID_TAG_ADR for the necessary clients on A02.
*/
#if ENABLE_AFI_DEVICE
/* Match AFIW */
mc_set_forced_coherent_so_dev_cfg(AFIR);
#endif
mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SDMMCWAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
mc_set_txn_override(GPUSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
/* See bug 200131110 comment #35*/
mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SDMMCRAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(GPUSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(GPUSRD2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(GPUSWR2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
/* See bug 200131110 comment #35*/
mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
/* See bug 200131110 comment #35 */
mc_set_txn_override(AFIR, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
/*
* See bug 200131110 comment #35 - there are no normal requests
* and AWID for SO/DEV requests is hardcoded in RTL for a
* particular PCIE controller
*/
#if ENABLE_AFI_DEVICE
mc_set_forced_coherent_so_dev_cfg(AFIW);
#endif
mc_set_forced_coherent_cfg(HDAR);
mc_set_forced_coherent_cfg(HDAW);
mc_set_forced_coherent_cfg(SATAR);
mc_set_forced_coherent_cfg(SATAW);
mc_set_forced_coherent_cfg(XUSB_HOSTR);
mc_set_forced_coherent_cfg(XUSB_HOSTW);
mc_set_forced_coherent_cfg(XUSB_DEVR);
mc_set_forced_coherent_cfg(XUSB_DEVW);
mc_set_forced_coherent_cfg(SDMMCRAB);
mc_set_forced_coherent_cfg(SDMMCWAB);
/* Match APEDMAW */
mc_set_forced_coherent_axid_so_dev_cfg(APEDMAR);
/*
* See bug 200131110 comment #35 - AWID for normal requests
* is 0x80 and AWID for SO/DEV requests is 0x01
*/
mc_set_forced_coherent_axid_so_dev_cfg(APEDMAW);
mc_set_forced_coherent_cfg(SESRD);
mc_set_forced_coherent_cfg(SESWR);
mc_set_forced_coherent_cfg(ETRR);
mc_set_forced_coherent_cfg(ETRW);
mc_set_forced_coherent_cfg(AXISR);
mc_set_forced_coherent_cfg(AXISW);
mc_set_forced_coherent_cfg(EQOSR);
mc_set_forced_coherent_cfg(EQOSW);
mc_set_forced_coherent_cfg(UFSHCR);
mc_set_forced_coherent_cfg(UFSHCW);
mc_set_forced_coherent_cfg(BPMPDMAR);
mc_set_forced_coherent_cfg(BPMPDMAW);
mc_set_forced_coherent_cfg(AONDMAR);
mc_set_forced_coherent_cfg(AONDMAW);
mc_set_forced_coherent_cfg(SCEDMAR);
mc_set_forced_coherent_cfg(SCEDMAW);
mc_set_txn_override(AFIW, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_COHERENT);
mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
/*
* At this point, ordering can occur at ROC. So, remove PCFIFO's
......@@ -192,56 +253,18 @@ static void tegra_memctrl_reconfig_mss_clients(void)
mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW) &
mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
/* EQOSW is the only client that has PCFIFO order enabled. */
val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val);
val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW);
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val);
/*
* At this point, ordering can occur at ROC. SMMU need not
* reorder any requests.
*
* Change SMMU_*_ORDERED_CLIENT from ORDERED -> UNORDERED
* for boot and strongly ordered MSS clients
*/
val = MC_SMMU_CLIENT_CONFIG1_RESET_VAL &
#if ENABLE_AFI_DEVICE
mc_set_smmu_unordered_boot_so_mss(1, AFIW) &
#endif
mc_set_smmu_unordered_boot_so_mss(1, HDAW) &
mc_set_smmu_unordered_boot_so_mss(1, SATAW);
tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG1, val);
val = MC_SMMU_CLIENT_CONFIG2_RESET_VAL &
mc_set_smmu_unordered_boot_so_mss(2, XUSB_HOSTW) &
mc_set_smmu_unordered_boot_so_mss(2, XUSB_DEVW);
tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG2, val);
val = MC_SMMU_CLIENT_CONFIG3_RESET_VAL &
mc_set_smmu_unordered_boot_so_mss(3, SDMMCWAB);
tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG3, val);
val = MC_SMMU_CLIENT_CONFIG4_RESET_VAL &
mc_set_smmu_unordered_boot_so_mss(4, SESWR) &
mc_set_smmu_unordered_boot_so_mss(4, ETRW) &
mc_set_smmu_unordered_boot_so_mss(4, AXISW) &
mc_set_smmu_unordered_boot_so_mss(4, EQOSW) &
mc_set_smmu_unordered_boot_so_mss(4, UFSHCW) &
mc_set_smmu_unordered_boot_so_mss(4, BPMPDMAW) &
mc_set_smmu_unordered_boot_so_mss(4, AONDMAW) &
mc_set_smmu_unordered_boot_so_mss(4, SCEDMAW);
tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG4, val);
val = MC_SMMU_CLIENT_CONFIG5_RESET_VAL &
mc_set_smmu_unordered_boot_so_mss(5, APEDMAW);
tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG5, val);
/*
* Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS
* clients to allow memory traffic from all clients to start passing
......
plat/nvidia/tegra/common/tegra_bl31_setup.c
View file @ af4aad2f
......@@ -27,6 +27,7 @@
#include <memctrl.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
/* length of Trusty's input parameters (in bytes) */
......@@ -122,6 +123,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
image_info_t bl32_img_info = { {0} };
uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
uint32_t console_clock;
/*
* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
......@@ -155,6 +157,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
/*
* It is very important that we run either from TZDRAM or TZSRAM base.
......@@ -164,6 +167,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
(TEGRA_TZRAM_BASE != BL31_BASE))
panic();
/*
* Reference clock used by the FPGAs is a lot slower.
*/
if (tegra_platform_is_fpga() == 1U) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
}
/*
* Get the base address of the UART controller to be used for the
* console
......@@ -174,8 +186,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/*
* Configure the UART port to be used as the console
*/
console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
TEGRA_CONSOLE_BAUDRATE);
console_init(tegra_console_base, console_clock,
TEGRA_CONSOLE_BAUDRATE);
}
/*
......@@ -239,6 +251,11 @@ void plat_trusty_set_boot_args(aapcs64_params_t *args)
args->arg0 = bl32_mem_size;
args->arg1 = bl32_boot_params;
args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
/* update EKS size */
if (args->arg4 != 0U) {
args->arg2 = args->arg4;
}
}
#endif
......
plat/nvidia/tegra/common/tegra_fiq_glue.c
View file @ af4aad2f
......@@ -41,6 +41,11 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
uint32_t cpu = plat_my_core_pos();
uint32_t irq;
(void)id;
(void)flags;
(void)handle;
(void)cookie;
bakery_lock_get(&tegra_fiq_lock);
/*
......
plat/nvidia/tegra/common/tegra_platform.c
View file @ af4aad2f
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <assert.h>
#include <lib/mmio.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
......@@ -19,35 +19,33 @@ typedef enum tegra_platform {
TEGRA_PLATFORM_QT,
TEGRA_PLATFORM_FPGA,
TEGRA_PLATFORM_EMULATION,
TEGRA_PLATFORM_LINSIM,
TEGRA_PLATFORM_UNIT_FPGA,
TEGRA_PLATFORM_VIRT_DEV_KIT,
TEGRA_PLATFORM_MAX,
} tegra_platform_t;
/*******************************************************************************
* Tegra macros defining all the SoC minor versions
******************************************************************************/
#define TEGRA_MINOR_QT 0
#define TEGRA_MINOR_FPGA 1
#define TEGRA_MINOR_EMULATION_MIN 2
#define TEGRA_MINOR_EMULATION_MAX 10
/*******************************************************************************
* Tegra major, minor version helper macros
******************************************************************************/
#define MAJOR_VERSION_SHIFT 0x4
#define MAJOR_VERSION_MASK 0xF
#define MINOR_VERSION_SHIFT 0x10
#define MINOR_VERSION_MASK 0xF
#define CHIP_ID_SHIFT 8
#define CHIP_ID_MASK 0xFF
#define TEGRA_MINOR_QT U(0)
#define TEGRA_MINOR_FPGA U(1)
#define TEGRA_MINOR_ASIM_QT U(2)
#define TEGRA_MINOR_ASIM_LINSIM U(3)
#define TEGRA_MINOR_DSIM_ASIM_LINSIM U(4)
#define TEGRA_MINOR_UNIT_FPGA U(5)
#define TEGRA_MINOR_VIRT_DEV_KIT U(6)
/*******************************************************************************
* Tegra chip ID values
* Tegra macros defining all the SoC pre_si_platform
******************************************************************************/
typedef enum tegra_chipid {
TEGRA_CHIPID_TEGRA13 = 0x13,
TEGRA_CHIPID_TEGRA21 = 0x21,
TEGRA_CHIPID_TEGRA18 = 0x18,
} tegra_chipid_t;
#define TEGRA_PRE_SI_QT U(1)
#define TEGRA_PRE_SI_FPGA U(2)
#define TEGRA_PRE_SI_UNIT_FPGA U(3)
#define TEGRA_PRE_SI_ASIM_QT U(4)
#define TEGRA_PRE_SI_ASIM_LINSIM U(5)
#define TEGRA_PRE_SI_DSIM_ASIM_LINSIM U(6)
#define TEGRA_PRE_SI_VDK U(8)
/*
* Read the chip ID value
......@@ -73,25 +71,38 @@ uint32_t tegra_get_chipid_minor(void)
return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK;
}
uint8_t tegra_chipid_is_t132(void)
/*
* Read the chip's pre_si_platform valus from the chip ID value
*/
static uint32_t tegra_get_chipid_pre_si_platform(void)
{
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK;
}
return (chip_id == TEGRA_CHIPID_TEGRA13);
bool tegra_chipid_is_t132(void)
{
uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA13);
}
uint8_t tegra_chipid_is_t210(void)
bool tegra_chipid_is_t186(void)
{
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
return (chip_id == TEGRA_CHIPID_TEGRA21);
return (chip_id == TEGRA_CHIPID_TEGRA18);
}
uint8_t tegra_chipid_is_t186(void)
bool tegra_chipid_is_t210(void)
{
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
return (chip_id == TEGRA_CHIPID_TEGRA18);
return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA21);
}
bool tegra_chipid_is_t210_b01(void)
{
return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2UL));
}
/*
......@@ -99,54 +110,152 @@ uint8_t tegra_chipid_is_t186(void)
*/
static tegra_platform_t tegra_get_platform(void)
{
uint32_t major = tegra_get_chipid_major();
uint32_t minor = tegra_get_chipid_minor();
uint32_t major, minor, pre_si_platform;
tegra_platform_t ret;
/* get the major/minor chip ID values */
major = tegra_get_chipid_major();
minor = tegra_get_chipid_minor();
pre_si_platform = tegra_get_chipid_pre_si_platform();
/* Actual silicon platforms have a non-zero major version */
if (major > 0)
return TEGRA_PLATFORM_SILICON;
if (major == 0U) {
/*
* The minor version number is used by simulation platforms
*/
switch (minor) {
/*
* Cadence's QuickTurn emulation system is a Solaris-based
* chip emulation system
*/
case TEGRA_MINOR_QT:
case TEGRA_MINOR_ASIM_QT:
ret = TEGRA_PLATFORM_QT;
break;
/*
* The minor version number is used by simulation platforms
*/
/*
* FPGAs are used during early software/hardware development
*/
case TEGRA_MINOR_FPGA:
ret = TEGRA_PLATFORM_FPGA;
break;
/*
* Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel
* simulation framework.
*/
case TEGRA_MINOR_ASIM_LINSIM:
case TEGRA_MINOR_DSIM_ASIM_LINSIM:
ret = TEGRA_PLATFORM_LINSIM;
break;
/*
* Cadence's QuickTurn emulation system is a Solaris-based
* chip emulation system
*/
if (minor == TEGRA_MINOR_QT)
return TEGRA_PLATFORM_QT;
/*
* Unit FPGAs run the actual hardware block IP on the FPGA with
* the other parts of the system using Linsim.
*/
case TEGRA_MINOR_UNIT_FPGA:
ret = TEGRA_PLATFORM_UNIT_FPGA;
break;
/*
* The Virtualizer Development Kit (VDK) is the standard chip
* development from Synopsis.
*/
case TEGRA_MINOR_VIRT_DEV_KIT:
ret = TEGRA_PLATFORM_VIRT_DEV_KIT;
break;
/*
* FPGAs are used during early software/hardware development
*/
if (minor == TEGRA_MINOR_FPGA)
return TEGRA_PLATFORM_FPGA;
default:
ret = TEGRA_PLATFORM_MAX;
break;
}
/* Minor version reserved for other emulation platforms */
if ((minor > TEGRA_MINOR_FPGA) && (minor <= TEGRA_MINOR_EMULATION_MAX))
return TEGRA_PLATFORM_EMULATION;
} else if (pre_si_platform > 0U) {
/* unsupported platform */
return TEGRA_PLATFORM_MAX;
switch (pre_si_platform) {
/*
* Cadence's QuickTurn emulation system is a Solaris-based
* chip emulation system
*/
case TEGRA_PRE_SI_QT:
case TEGRA_PRE_SI_ASIM_QT:
ret = TEGRA_PLATFORM_QT;
break;
/*
* FPGAs are used during early software/hardware development
*/
case TEGRA_PRE_SI_FPGA:
ret = TEGRA_PLATFORM_FPGA;
break;
/*
* Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel
* simulation framework.
*/
case TEGRA_PRE_SI_ASIM_LINSIM:
case TEGRA_PRE_SI_DSIM_ASIM_LINSIM:
ret = TEGRA_PLATFORM_LINSIM;
break;
/*
* Unit FPGAs run the actual hardware block IP on the FPGA with
* the other parts of the system using Linsim.
*/
case TEGRA_PRE_SI_UNIT_FPGA:
ret = TEGRA_PLATFORM_UNIT_FPGA;
break;
/*
* The Virtualizer Development Kit (VDK) is the standard chip
* development from Synopsis.
*/
case TEGRA_PRE_SI_VDK:
ret = TEGRA_PLATFORM_VIRT_DEV_KIT;
break;
default:
ret = TEGRA_PLATFORM_MAX;
break;
}
} else {
/* Actual silicon platforms have a non-zero major version */
ret = TEGRA_PLATFORM_SILICON;
}
return ret;
}
uint8_t tegra_platform_is_silicon(void)
bool tegra_platform_is_silicon(void)
{
return (tegra_get_platform() == TEGRA_PLATFORM_SILICON);
return ((tegra_get_platform() == TEGRA_PLATFORM_SILICON) ? true : false);
}
uint8_t tegra_platform_is_qt(void)
bool tegra_platform_is_qt(void)
{
return (tegra_get_platform() == TEGRA_PLATFORM_QT);
return ((tegra_get_platform() == TEGRA_PLATFORM_QT) ? true : false);
}
uint8_t tegra_platform_is_fpga(void)
bool tegra_platform_is_linsim(void)
{
return (tegra_get_platform() == TEGRA_PLATFORM_FPGA);
tegra_platform_t plat = tegra_get_platform();
return (((plat == TEGRA_PLATFORM_LINSIM) ||
(plat == TEGRA_PLATFORM_UNIT_FPGA)) ? true : false);
}
uint8_t tegra_platform_is_emulation(void)
bool tegra_platform_is_fpga(void)
{
return ((tegra_get_platform() == TEGRA_PLATFORM_FPGA) ? true : false);
}
bool tegra_platform_is_emulation(void)
{
return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION);
}
bool tegra_platform_is_unit_fpga(void)
{
return ((tegra_get_platform() == TEGRA_PLATFORM_UNIT_FPGA) ? true : false);
}
bool tegra_platform_is_virt_dev_kit(void)
{
return ((tegra_get_platform() == TEGRA_PLATFORM_VIRT_DEV_KIT) ? true : false);
}
plat/nvidia/tegra/common/tegra_pm.c
View file @ af4aad2f
......@@ -21,6 +21,7 @@
#include <memctrl.h>
#include <pmc.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
extern uint64_t tegra_bl31_phys_base;
......@@ -222,6 +223,7 @@ __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
plat_params_from_bl2_t *plat_params;
uint32_t console_clock;
/*
* Initialize the GIC cpu and distributor interfaces
......@@ -234,10 +236,19 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PSTATE_ID_SOC_POWERDN) {
/*
* Reference clock used by the FPGAs is a lot slower.
*/
if (tegra_platform_is_fpga() == 1U) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
}
/* Initialize the runtime console */
if (tegra_console_base != (uint64_t)0) {
console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
TEGRA_CONSOLE_BAUDRATE);
console_init(tegra_console_base, console_clock,
TEGRA_CONSOLE_BAUDRATE);
}
/*
......
plat/nvidia/tegra/common/tegra_sip_calls.c
View file @ af4aad2f
......@@ -31,20 +31,29 @@
******************************************************************************/
extern uint8_t tegra_fake_system_suspend;
/*******************************************************************************
* SoC specific SiP handler
******************************************************************************/
#pragma weak plat_sip_handler
int plat_sip_handler(uint32_t smc_fid,
int32_t plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
const void *cookie,
void *handle,
uint64_t flags)
{
/* unused parameters */
(void)smc_fid;
(void)x1;
(void)x2;
(void)x3;
(void)x4;
(void)cookie;
(void)handle;
(void)flags;
return -ENOTSUP;
}
......@@ -61,112 +70,115 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
u_register_t flags)
{
uint32_t regval;
int err;
int32_t err;
/* Check if this is a SoC specific SiP */
err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
if (err == 0)
SMC_RET1(handle, (uint64_t)err);
switch (smc_fid) {
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
/* clean up the high bits */
x2 = (uint32_t)x2;
/*
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
* or falls outside of the valid DRAM range
*/
err = bl31_check_ns_address(x1, x2);
if (err)
SMC_RET1(handle, err);
/*
* Check if Video Memory is aligned to 1MB.
*/
if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
ERROR("Unaligned Video Memory base address!\n");
SMC_RET1(handle, -ENOTSUP);
}
/*
* The GPU is the user of the Video Memory region. In order to
* transition to the new memory region smoothly, we program the
* new base/size ONLY if the GPU is in reset mode.
*/
regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
TEGRA_GPU_RESET_REG_OFFSET);
if ((regval & GPU_RESET_BIT) == 0U) {
ERROR("GPU not in reset! Video Memory setup failed\n");
SMC_RET1(handle, -ENOTSUP);
}
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, x2);
if (err == 0) {
SMC_RET1(handle, 0);
break;
SMC_RET1(handle, (uint64_t)err);
/*
* The NS world registers the address of its handler to be
* used for processing the FIQ. This is normally used by the
* NS FIQ debugger driver to detect system hangs by programming
* a watchdog timer to fire a FIQ interrupt.
*/
case TEGRA_SIP_FIQ_NS_ENTRYPOINT:
} else {
switch (smc_fid) {
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
/* clean up the high bits */
x2 = (uint32_t)x2;
/*
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
* or falls outside of the valid DRAM range
*/
err = bl31_check_ns_address(x1, x2);
if (err != 0) {
SMC_RET1(handle, (uint64_t)err);
}
/*
* Check if Video Memory is aligned to 1MB.
*/
if (((x1 & 0xFFFFFU) != 0U) || ((x2 & 0xFFFFFU) != 0U)) {
ERROR("Unaligned Video Memory base address!\n");
SMC_RET1(handle, -ENOTSUP);
}
/*
* The GPU is the user of the Video Memory region. In order to
* transition to the new memory region smoothly, we program the
* new base/size ONLY if the GPU is in reset mode.
*/
regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
TEGRA_GPU_RESET_REG_OFFSET);
if ((regval & GPU_RESET_BIT) == 0UL) {
ERROR("GPU not in reset! Video Memory setup failed\n");
SMC_RET1(handle, -ENOTSUP);
}
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, (uint32_t)x2);
if (!x1)
SMC_RET1(handle, SMC_UNK);
SMC_RET1(handle, 0);
/*
* TODO: Check if x1 contains a valid DRAM address
* The NS world registers the address of its handler to be
* used for processing the FIQ. This is normally used by the
* NS FIQ debugger driver to detect system hangs by programming
* a watchdog timer to fire a FIQ interrupt.
*/
case TEGRA_SIP_FIQ_NS_ENTRYPOINT:
/* store the NS world's entrypoint */
tegra_fiq_set_ns_entrypoint(x1);
SMC_RET1(handle, 0);
break;
if (x1 == 0U) {
SMC_RET1(handle, SMC_UNK);
}
/*
* The NS world's FIQ handler issues this SMC to get the NS EL1/EL0
* CPU context when the FIQ interrupt was triggered. This allows the
* NS world to understand the CPU state when the watchdog interrupt
* triggered.
*/
case TEGRA_SIP_FIQ_NS_GET_CONTEXT:
/*
* TODO: Check if x1 contains a valid DRAM address
*/
/* retrieve context registers when FIQ triggered */
tegra_fiq_get_intr_context();
/* store the NS world's entrypoint */
tegra_fiq_set_ns_entrypoint(x1);
SMC_RET0(handle);
break;
case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND:
/*
* System suspend fake mode is set if we are on VDK and we make
* a debug SIP call. This mode ensures that we excercise debug
* path instead of the regular code path to suit the pre-silicon
* platform needs. These include replacing the call to WFI by
* a warm reset request.
*/
if (tegra_platform_is_emulation() != 0U) {
tegra_fake_system_suspend = 1;
SMC_RET1(handle, 0);
}
/*
* We return to the external world as if this SIP is not
* implemented in case, we are not running on VDK.
* The NS world's FIQ handler issues this SMC to get the NS EL1/EL0
* CPU context when the FIQ interrupt was triggered. This allows the
* NS world to understand the CPU state when the watchdog interrupt
* triggered.
*/
break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
case TEGRA_SIP_FIQ_NS_GET_CONTEXT:
/* retrieve context registers when FIQ triggered */
(void)tegra_fiq_get_intr_context();
SMC_RET0(handle);
case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND:
/*
* System suspend fake mode is set if we are on VDK and we make
* a debug SIP call. This mode ensures that we excercise debug
* path instead of the regular code path to suit the pre-silicon
* platform needs. These include replacing the call to WFI by
* a warm reset request.
*/
if (tegra_platform_is_virt_dev_kit() != false) {
tegra_fake_system_suspend = 1;
SMC_RET1(handle, 0);
}
/*
* We return to the external world as if this SIP is not
* implemented in case, we are not running on VDK.
*/
break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
}
}
SMC_RET1(handle, SMC_UNK);
......@@ -176,9 +188,9 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
DECLARE_RT_SVC(
tegra_sip_fast,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
NULL,
tegra_sip_handler
(OEN_SIP_START),
(OEN_SIP_END),
(SMC_TYPE_FAST),
(NULL),
(tegra_sip_handler)
);
plat/nvidia/tegra/common/tegra_topology.c
View file @ af4aad2f
......@@ -7,41 +7,38 @@
#include <platform_def.h>
#include <arch.h>
#include <platform.h>
#include <lib/psci/psci.h>
extern const unsigned char tegra_power_domain_tree_desc[];
#pragma weak plat_core_pos_by_mpidr
/*******************************************************************************
* This function returns the Tegra default topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return tegra_power_domain_tree_desc;
}
/*******************************************************************************
* This function implements a part of the critical interface between the psci
* generic layer and the platform that allows the former to query the platform
* to convert an MPIDR to a unique linear index. An error code (-1) is returned
* in case the MPIDR is invalid.
******************************************************************************/
int plat_core_pos_by_mpidr(u_register_t mpidr)
int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
{
unsigned int cluster_id, cpu_id;
u_register_t cluster_id, cpu_id;
int32_t result;
cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
result = (int32_t)cpu_id + ((int32_t)cluster_id * 4);
if (cluster_id >= PLATFORM_CLUSTER_COUNT)
return PSCI_E_NOT_PRESENT;
if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) {
result = PSCI_E_NOT_PRESENT;
}
/*
* Validate cpu_id by checking whether it represents a CPU in
* one of the two clusters present on the platform.
*/
if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
return PSCI_E_NOT_PRESENT;
if (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER) {
result = PSCI_E_NOT_PRESENT;
}
return (cpu_id + (cluster_id * 4));
return result;
}
plat/nvidia/tegra/include/drivers/bpmp.h 0 → 100644
View file @ af4aad2f
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BPMP_H
#define BPMP_H
#include <stdint.h>
/* macro to enable clock to the Atomics block */
#define CAR_ENABLE_ATOMICS (1UL << 16)
/* command to get the channel base addresses from bpmp */
#define ATOMIC_CMD_GET 4UL
/* Hardware IRQ # used to signal bpmp of an incoming command */
#define INT_SHR_SEM_OUTBOX_FULL 6UL
/* macros to decode the bpmp's state */
#define CH_MASK(ch) (0x3UL << ((ch) * 2UL))
#define MA_FREE(ch) (0x2UL << ((ch) * 2UL))
#define MA_ACKD(ch) (0x3UL << ((ch) * 2UL))
/* response from bpmp to indicate it has powered up */
#define SIGN_OF_LIFE 0xAAAAAAAAUL
/* flags to indicate bpmp driver's state */
#define BPMP_INIT_COMPLETE 0xBEEFF00DUL
#define BPMP_INIT_PENDING 0xDEADBEEFUL
/* requests serviced by the bpmp */
#define MRQ_PING 0
#define MRQ_QUERY_TAG 1
#define MRQ_DO_IDLE 2
#define MRQ_TOLERATE_IDLE 3
#define MRQ_MODULE_LOAD 4
#define MRQ_MODULE_UNLOAD 5
#define MRQ_SWITCH_CLUSTER 6
#define MRQ_TRACE_MODIFY 7
#define MRQ_WRITE_TRACE 8
#define MRQ_THREADED_PING 9
#define MRQ_CPUIDLE_USAGE 10
#define MRQ_MODULE_MAIL 11
#define MRQ_SCX_ENABLE 12
#define MRQ_BPMPIDLE_USAGE 14
#define MRQ_HEAP_USAGE 15
#define MRQ_SCLK_SKIP_SET_RATE 16
#define MRQ_ENABLE_SUSPEND 17
#define MRQ_PASR_MASK 18
#define MRQ_DEBUGFS 19
#define MRQ_THERMAL 27
/* Tegra PM states as known to BPMP */
#define TEGRA_PM_CC1 9
#define TEGRA_PM_CC4 12
#define TEGRA_PM_CC6 14
#define TEGRA_PM_CC7 15
#define TEGRA_PM_SC1 17
#define TEGRA_PM_SC2 18
#define TEGRA_PM_SC3 19
#define TEGRA_PM_SC4 20
#define TEGRA_PM_SC7 23
/* flag to indicate if entry into a CCx power state is allowed */
#define BPMP_CCx_ALLOWED 0UL
/* number of communication channels to interact with the bpmp */
#define NR_CHANNELS 4U
/* flag to ask bpmp to acknowledge command packet */
#define NO_ACK (0UL << 0UL)
#define DO_ACK (1UL << 0UL)
/* size of the command/response data */
#define MSG_DATA_MAX_SZ 120U
/**
* command/response packet to/from the bpmp
*
* command
* -------
* code: MRQ_* command
* flags: DO_ACK or NO_ACK
* data:
* [0] = cpu #
* [1] = cluster power state (TEGRA_PM_CCx)
* [2] = system power state (TEGRA_PM_SCx)
*
* response
* ---------
* code: error code
* flags: not used
* data:
* [0-3] = response value
*/
typedef struct mb_data {
int32_t code;
uint32_t flags;
uint8_t data[MSG_DATA_MAX_SZ];
} mb_data_t;
/**
* Function to initialise the interface with the bpmp
*/
int tegra_bpmp_init(void);
/**
* Handler to send a MRQ_* command to the bpmp
*/
int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
void *ib_data, int ib_sz);
#endif /* BPMP_H */
plat/nvidia/tegra/include/drivers/memctrl_v2.h
View file @ af4aad2f
......@@ -100,6 +100,19 @@
******************************************************************************/
#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t))
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0UL << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1UL << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2UL << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3UL << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0UL << 8)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1UL << 8)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2UL << 8)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3UL << 8)
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0UL << 12)
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1UL << 12)
/*******************************************************************************
* Memory Controller transaction override config registers
******************************************************************************/
......@@ -312,98 +325,51 @@ typedef struct tegra_mc_settings {
/*******************************************************************************
* Memory Controller's PCFIFO client configuration registers
******************************************************************************/
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0 << 17)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1 << 17)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0 << 21)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1 << 21)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0 << 29)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1 << 29)
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0 << 11)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1 << 11)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0 << 13)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1 << 13)
#define MC_PCFIFO_CLIENT_CONFIG3 0xddc
#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0 << 7)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1 << 7)
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0
#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0 << 1)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1 << 1)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0 << 5)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1 << 5)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0 << 13)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1 << 13)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0 << 15)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1 << 15)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0 << 17)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1 << 17)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0 << 22)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1 << 22)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0 << 26)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1 << 26)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0 << 30)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1 << 30)
#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4
#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0 << 0)
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1 << 0)
/*******************************************************************************
* Memory Controller's SMMU client configuration registers
******************************************************************************/
#define MC_SMMU_CLIENT_CONFIG1 0x44
#define MC_SMMU_CLIENT_CONFIG1_RESET_VAL 0x20000
#define MC_SMMU_CLIENT_CONFIG1_AFIW_UNORDERED (0 << 17)
#define MC_SMMU_CLIENT_CONFIG1_AFIW_MASK (1 << 17)
#define MC_SMMU_CLIENT_CONFIG1_HDAW_UNORDERED (0 << 21)
#define MC_SMMU_CLIENT_CONFIG1_HDAW_MASK (1 << 21)
#define MC_SMMU_CLIENT_CONFIG1_SATAW_UNORDERED (0 << 29)
#define MC_SMMU_CLIENT_CONFIG1_SATAW_MASK (1 << 29)
#define MC_SMMU_CLIENT_CONFIG2 0x48
#define MC_SMMU_CLIENT_CONFIG2_RESET_VAL 0x20000
#define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_UNORDERED (0 << 11)
#define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_MASK (1 << 11)
#define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_UNORDERED (0 << 13)
#define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_MASK (1 << 13)
#define MC_SMMU_CLIENT_CONFIG3 0x4c
#define MC_SMMU_CLIENT_CONFIG3_RESET_VAL 0
#define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_UNORDERED (0 << 7)
#define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_MASK (1 << 7)
#define MC_SMMU_CLIENT_CONFIG4 0xb9c
#define MC_SMMU_CLIENT_CONFIG4_RESET_VAL 0
#define MC_SMMU_CLIENT_CONFIG4_SESWR_UNORDERED (0 << 1)
#define MC_SMMU_CLIENT_CONFIG4_SESWR_MASK (1 << 1)
#define MC_SMMU_CLIENT_CONFIG4_ETRW_UNORDERED (0 << 5)
#define MC_SMMU_CLIENT_CONFIG4_ETRW_MASK (1 << 5)
#define MC_SMMU_CLIENT_CONFIG4_AXISW_UNORDERED (0 << 13)
#define MC_SMMU_CLIENT_CONFIG4_AXISW_MASK (1 << 13)
#define MC_SMMU_CLIENT_CONFIG4_EQOSW_UNORDERED (0 << 15)
#define MC_SMMU_CLIENT_CONFIG4_EQOSW_MASK (1 << 15)
#define MC_SMMU_CLIENT_CONFIG4_UFSHCW_UNORDERED (0 << 17)
#define MC_SMMU_CLIENT_CONFIG4_UFSHCW_MASK (1 << 17)
#define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_UNORDERED (0 << 22)
#define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_MASK (1 << 22)
#define MC_SMMU_CLIENT_CONFIG4_AONDMAW_UNORDERED (0 << 26)
#define MC_SMMU_CLIENT_CONFIG4_AONDMAW_MASK (1 << 26)
#define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_UNORDERED (0 << 30)
#define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_MASK (1 << 30)
#define MC_SMMU_CLIENT_CONFIG5 0xbac
#define MC_SMMU_CLIENT_CONFIG5_RESET_VAL 0
#define MC_SMMU_CLIENT_CONFIG5_APEDMAW_UNORDERED (0 << 0)
#define MC_SMMU_CLIENT_CONFIG5_APEDMAW_MASK (1 << 0)
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4UL
#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000UL
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0UL << 17)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1UL << 17)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0UL << 21)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1UL << 21)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0UL << 29)
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1UL << 29)
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8UL
#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000UL
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0UL << 11)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1UL << 11)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0UL << 13)
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1UL << 13)
#define MC_PCFIFO_CLIENT_CONFIG3 0xddcUL
#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0UL
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0UL << 7)
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1UL << 7)
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0UL
#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0UL
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0UL << 1)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1UL << 1)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0UL << 5)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1UL << 5)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0UL << 13)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1UL << 13)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0UL << 15)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1UL << 15)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1UL << 15)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0UL << 17)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1UL << 17)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0UL << 22)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1UL << 22)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0UL << 26)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1UL << 26)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0UL << 30)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1UL << 30)
#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4UL
#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0UL
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0UL << 0)
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1UL << 0)
#ifndef __ASSEMBLY__
......@@ -433,9 +399,8 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
(~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
#define mc_set_smmu_unordered_boot_so_mss(id, client) \
(~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
#define mc_set_tsa_passthrough(client) \
{ \
......@@ -445,25 +410,13 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
}
#define mc_set_forced_coherent_cfg(client) \
{ \
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV); \
}
#define mc_set_forced_coherent_so_dev_cfg(client) \
{ \
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \
}
#define mc_set_forced_coherent_axid_so_dev_cfg(client) \
#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
{ \
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \
MC_TXN_OVERRIDE_##normal_axi_id | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
}
/*******************************************************************************
......
plat/nvidia/tegra/include/drivers/security_engine.h 0 → 100644
View file @ af4aad2f
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SECURITY_ENGINE_H
#define SECURITY_ENGINE_H
/*******************************************************************************
* Structure definition
******************************************************************************/
/* Security Engine Linked List */
struct tegra_se_ll {
/* DMA buffer address */
uint32_t addr;
/* Data length in DMA buffer */
uint32_t data_len;
};
#define SE_LL_MAX_BUFFER_NUM 4
typedef struct tegra_se_io_lst {
volatile uint32_t last_buff_num;
volatile struct tegra_se_ll buffer[SE_LL_MAX_BUFFER_NUM];
} tegra_se_io_lst_t __attribute__((aligned(4)));
/* SE device structure */
typedef struct tegra_se_dev {
/* Security Engine ID */
const int se_num;
/* SE base address */
const uint64_t se_base;
/* SE context size in AES blocks */
const uint32_t ctx_size_blks;
/* pointer to source linked list buffer */
tegra_se_io_lst_t *src_ll_buf;
/* pointer to destination linked list buffer */
tegra_se_io_lst_t *dst_ll_buf;
} tegra_se_dev_t;
/*******************************************************************************
* Public interface
******************************************************************************/
void tegra_se_init(void);
int tegra_se_suspend(void);
void tegra_se_resume(void);
int tegra_se_save_tzram(void);
#endif /* SECURITY_ENGINE_H */
plat/nvidia/tegra/include/platform_def.h
View file @ af4aad2f
......@@ -34,7 +34,8 @@
* Platform console related constants
******************************************************************************/
#define TEGRA_CONSOLE_BAUDRATE U(115200)
#define TEGRA_BOOT_UART_CLK_IN_HZ U(408000000)
#define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000)
#define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000)
/*******************************************************************************
* Platform memory map related constants
......
plat/nvidia/tegra/include/t210/tegra_def.h
View file @ af4aad2f
......@@ -32,6 +32,11 @@
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/*******************************************************************************
* iRAM memory constants
******************************************************************************/
#define TEGRA_IRAM_BASE 0x40000000
/*******************************************************************************
* GIC memory map
******************************************************************************/
......@@ -55,6 +60,20 @@
ENABLE_WRAP_INCR_MASTER1_BIT | \
ENABLE_WRAP_INCR_MASTER0_BIT)
/*******************************************************************************
* Tegra Resource Semaphore constants
******************************************************************************/
#define TEGRA_RES_SEMA_BASE 0x60001000UL
#define STA_OFFSET 0UL
#define SET_OFFSET 4UL
#define CLR_OFFSET 8UL
/*******************************************************************************
* Tegra Primary Interrupt Controller constants
******************************************************************************/
#define TEGRA_PRI_ICTLR_BASE 0x60004000UL
#define CPU_IEP_FIR_SET 0x18UL
/*******************************************************************************
* Tegra micro-seconds timer constants
******************************************************************************/
......@@ -67,12 +86,19 @@
#define TEGRA_CAR_RESET_BASE U(0x60006000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
#define GPU_RESET_BIT (U(1) << 24)
#define TEGRA_RST_DEV_CLR_V U(0x434)
#define TEGRA_CLK_ENB_V U(0x440)
/*******************************************************************************
* Tegra Flow Controller constants
******************************************************************************/
#define TEGRA_FLOWCTRL_BASE U(0x60007000)
/*******************************************************************************
* Tegra AHB arbitration controller
******************************************************************************/
#define TEGRA_AHB_ARB_BASE 0x6000C000UL
/*******************************************************************************
* Tegra Secure Boot Controller constants
******************************************************************************/
......@@ -103,6 +129,15 @@
******************************************************************************/
#define TEGRA_PMC_BASE U(0x7000E400)
/*******************************************************************************
* Tegra Atomics constants
******************************************************************************/
#define TEGRA_ATOMICS_BASE 0x70016000UL
#define TRIGGER0_REG_OFFSET 0UL
#define TRIGGER_WIDTH_SHIFT 4UL
#define TRIGGER_ID_SHIFT 16UL
#define RESULT0_REG_OFFSET 0xC00UL
/*******************************************************************************
* Tegra Memory Controller constants
******************************************************************************/
......@@ -118,6 +153,15 @@
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
/*******************************************************************************
* Tegra SE constants
******************************************************************************/
#define TEGRA_SE1_BASE U(0x70012000)
#define TEGRA_SE2_BASE U(0x70412000)
#define TEGRA_PKA1_BASE U(0x70420000)
#define TEGRA_SE2_RANGE_SIZE U(0x2000)
#define SE_TZRAM_SECURITY U(0x4)
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
......
plat/nvidia/tegra/include/tegra_platform.h
View file @ af4aad2f
......@@ -8,27 +8,56 @@
#define TEGRA_PLATFORM_H
#include <cdefs.h>
#include <stdbool.h>
#include <utils_def.h>
/*******************************************************************************
* Tegra major, minor version helper macros
******************************************************************************/
#define MAJOR_VERSION_SHIFT U(0x4)
#define MAJOR_VERSION_MASK U(0xF)
#define MINOR_VERSION_SHIFT U(0x10)
#define MINOR_VERSION_MASK U(0xF)
#define CHIP_ID_SHIFT U(8)
#define CHIP_ID_MASK U(0xFF)
#define PRE_SI_PLATFORM_SHIFT U(0x14)
#define PRE_SI_PLATFORM_MASK U(0xF)
/*******************************************************************************
* Tegra chip ID values
******************************************************************************/
#define TEGRA_CHIPID_TEGRA13 U(0x13)
#define TEGRA_CHIPID_TEGRA21 U(0x21)
#define TEGRA_CHIPID_TEGRA18 U(0x18)
#ifndef __ASSEMBLY__
/*
* Tegra chip major/minor version
* Tegra chip ID major/minor identifiers
*/
uint32_t tegra_get_chipid_major(void);
uint32_t tegra_get_chipid_minor(void);
/*
* Tegra chip identifiers
* Tegra chip ID identifiers
*/
uint8_t tegra_chipid_is_t132(void);
uint8_t tegra_chipid_is_t210(void);
uint8_t tegra_chipid_is_t186(void);
bool tegra_chipid_is_t132(void);
bool tegra_chipid_is_t186(void);
bool tegra_chipid_is_t210(void);
bool tegra_chipid_is_t210_b01(void);
/*
* Tegra platform identifiers
*/
uint8_t tegra_platform_is_silicon(void);
uint8_t tegra_platform_is_qt(void);
uint8_t tegra_platform_is_emulation(void);
uint8_t tegra_platform_is_fpga(void);
bool tegra_platform_is_silicon(void);
bool tegra_platform_is_qt(void);
bool tegra_platform_is_emulation(void);
bool tegra_platform_is_linsim(void);
bool tegra_platform_is_fpga(void);
bool tegra_platform_is_unit_fpga(void);
bool tegra_platform_is_virt_dev_kit(void);
#endif /* __ASSEMBLY__ */
#endif /* TEGRA_PLATFORM_H */
plat/nvidia/tegra/include/tegra_private.h
View file @ af4aad2f
......@@ -32,8 +32,15 @@ typedef struct plat_params_from_bl2 {
uint64_t tzdram_base;
/* UART port ID */
int uart_id;
/* L2 ECC parity protection disable flag */
int l2_ecc_parity_prot_dis;
} plat_params_from_bl2_t;
/*******************************************************************************
* Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs
******************************************************************************/
DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
/*******************************************************************************
* Struct describing parameters passed to bl31
******************************************************************************/
......@@ -47,19 +54,19 @@ struct tegra_bl31_params {
};
/* Declarations for plat_psci_handlers.c */
int32_t tegra_soc_validate_power_state(unsigned int power_state,
int32_t tegra_soc_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state);
/* Declarations for plat_setup.c */
const mmap_region_t *plat_get_mmio_map(void);
uint32_t plat_get_console_from_id(int id);
uint32_t plat_get_console_from_id(int32_t id);
void plat_gic_setup(void);
struct tegra_bl31_params *plat_get_bl31_params(void);
plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
/* Declarations for plat_secondary.c */
void plat_secondary_setup(void);
int plat_lock_cpu_vectors(void);
int32_t plat_lock_cpu_vectors(void);
/* Declarations for tegra_fiq_glue.c */
void tegra_fiq_handler_setup(void);
......@@ -92,4 +99,22 @@ void tegra_delay_timer_init(void);
void tegra_secure_entrypoint(void);
void tegra186_cpu_reset_handler(void);
/* Declarations for tegra_sip_calls.c */
uintptr_t tegra_sip_handler(uint32_t smc_fid,
u_register_t x1,
u_register_t x2,
u_register_t x3,
u_register_t x4,
void *cookie,
void *handle,
u_register_t flags);
int plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
const void *cookie,
void *handle,
uint64_t flags);
#endif /* TEGRA_PRIVATE_H */
plat/nvidia/tegra/soc/t132/plat_setup.c
View file @ af4aad2f
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -7,25 +7,10 @@
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <platform.h>
#include <tegra_def.h>
#include <tegra_private.h>
/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
* single root node. The first entry in the power domain descriptor specifies
* the number of power domains at the highest power level.
*******************************************************************************
*/
const unsigned char tegra_power_domain_tree_desc[] = {
/* No of root nodes */
1,
/* No of clusters */
PLATFORM_CLUSTER_COUNT,
/* No of CPU cores */
PLATFORM_CORE_COUNT,
};
/* sets of MMIO ranges setup */
#define MMIO_RANGE_0_ADDR 0x50000000
#define MMIO_RANGE_1_ADDR 0x60000000
......@@ -54,6 +39,29 @@ const mmap_region_t *plat_get_mmio_map(void)
return tegra_mmap;
}
/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
* single root node. The first entry in the power domain descriptor specifies
* the number of power domains at the highest power level.
*******************************************************************************
*/
const unsigned char tegra_power_domain_tree_desc[] = {
/* No of root nodes */
1,
/* No of clusters */
PLATFORM_CLUSTER_COUNT,
/* No of CPU cores */
PLATFORM_CORE_COUNT,
};
/*******************************************************************************
* This function returns the Tegra default topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return tegra_power_domain_tree_desc;
}
unsigned int plat_get_syscnt_freq2(void)
{
return 12000000;
......
plat/nvidia/tegra/soc/t132/plat_sip_calls.c
View file @ af4aad2f
......@@ -38,7 +38,7 @@ int plat_sip_handler(uint32_t smc_fid,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
const void *cookie,
void *handle,
uint64_t flags)
{
......
plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
View file @ af4aad2f
......@@ -99,9 +99,9 @@ static int32_t ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t r
ret = 0;
} else {
/* For shutdown/reboot commands, we dont have to check for timeouts */
if ((req == (uint32_t)TEGRA_ARI_MISC_CCPLEX) &&
((lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) ||
(lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) {
if ((req == TEGRA_ARI_MISC_CCPLEX) &&
((lo == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) ||
(lo == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) {
ret = 0;
} else {
/*
......@@ -161,38 +161,38 @@ int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccp
uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
uint8_t update_wake_mask)
{
uint32_t val = 0U;
uint64_t val = 0U;
/* clean the previous response state */
ari_clobber_response(ari_base);
/* update CLUSTER_CSTATE? */
if (cluster != 0U) {
val |= (cluster & (uint32_t)CLUSTER_CSTATE_MASK) |
(uint32_t)CLUSTER_CSTATE_UPDATE_BIT;
val |= (cluster & CLUSTER_CSTATE_MASK) |
CLUSTER_CSTATE_UPDATE_BIT;
}
/* update CCPLEX_CSTATE? */
if (ccplex != 0U) {
val |= ((ccplex & (uint32_t)CCPLEX_CSTATE_MASK) << (uint32_t)CCPLEX_CSTATE_SHIFT) |
(uint32_t)CCPLEX_CSTATE_UPDATE_BIT;
val |= ((ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) |
CCPLEX_CSTATE_UPDATE_BIT;
}
/* update SYSTEM_CSTATE? */
if (system != 0U) {
val |= ((system & (uint32_t)SYSTEM_CSTATE_MASK) << (uint32_t)SYSTEM_CSTATE_SHIFT) |
(((uint32_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
(uint32_t)SYSTEM_CSTATE_UPDATE_BIT);
val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
(((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
SYSTEM_CSTATE_UPDATE_BIT);
}
/* update wake mask value? */
if (update_wake_mask != 0U) {
val |= (uint32_t)CSTATE_WAKE_MASK_UPDATE_BIT;
val |= CSTATE_WAKE_MASK_UPDATE_BIT;
}
/* set the updated cstate info */
return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO, val,
wake_mask);
return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO,
(uint32_t)val, wake_mask);
}
int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
......@@ -299,10 +299,8 @@ int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time
int32_t ret, result;
/* check for allowed power state */
if ((state != TEGRA_ARI_CORE_C0) &&
(state != TEGRA_ARI_CORE_C1) &&
(state != TEGRA_ARI_CORE_C6) &&
(state != TEGRA_ARI_CORE_C7)) {
if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) &&
(state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) {
ERROR("%s: unknown cstate (%d)\n", __func__, state);
result = EINVAL;
} else {
......@@ -325,10 +323,10 @@ int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time
int32_t ari_online_core(uint32_t ari_base, uint32_t core)
{
uint64_t cpu = read_mpidr() & (uint64_t)(MPIDR_CPU_MASK);
uint64_t cluster = (read_mpidr() & (uint64_t)(MPIDR_CLUSTER_MASK)) >>
(uint64_t)(MPIDR_AFFINITY_BITS);
uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
uint64_t cpu = read_mpidr() & (MPIDR_CPU_MASK);
uint64_t cluster = (read_mpidr() & (MPIDR_CLUSTER_MASK)) >>
(MPIDR_AFFINITY_BITS);
uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
int32_t ret;
/* construct the current CPU # */
......@@ -342,8 +340,7 @@ int32_t ari_online_core(uint32_t ari_base, uint32_t core)
/*
* The Denver cluster has 2 CPUs only - 0, 1.
*/
if ((impl == (uint32_t)DENVER_IMPL) &&
((core == 2U) || (core == 3U))) {
if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) {
ERROR("%s: unknown core id (%d)\n", __func__, core);
ret = EINVAL;
} else {
......@@ -465,7 +462,7 @@ int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx)
{
int32_t ret = 0;
/* sanity check GSC ID */
if (gsc_idx > (uint32_t)TEGRA_ARI_GSC_VPR_IDX) {
if (gsc_idx > TEGRA_ARI_GSC_VPR_IDX) {
ret = EINVAL;
} else {
/* clean the previous response state */
......@@ -497,8 +494,8 @@ int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req,
uint64_t *data)
{
int32_t ret, result;
uint32_t val;
uint8_t req_cmd, req_status;
uint32_t val, req_status;
uint8_t req_cmd;
req_cmd = (uint8_t)(req >> UNCORE_PERFMON_CMD_SHIFT);
......@@ -523,7 +520,7 @@ int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req,
result = ret;
} else {
/* read the command status value */
req_status = (uint8_t)ari_get_response_high(ari_base) &
req_status = ari_get_response_high(ari_base) &
UNCORE_PERFMON_RESP_STATUS_MASK;
/*
......
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