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Unverified Commit c40c88f8 authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
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Merge pull request #1764 from vwadekar/tf2.0-tegra-downstream-rebase-1.7.19 

Tf2.0 tegra downstream rebase 1.7.19
parents fbf35335 650d9c52
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docs/plat/nvidia-tegra.rst
View file @ c40c88f8
......@@ -82,6 +82,8 @@ uint64\_t tzdram\_base;
int uart\_id;
/* L2 ECC parity protection disable flag \*/
int l2\_ecc\_parity\_prot\_dis;
/* SHMEM base address for storing the boot logs \*/
uint64\_t boot\_profiler\_shmem\_base;
} plat\_params\_from\_bl2\_t;
Power Management
......
plat/nvidia/tegra/common/aarch64/tegra_helpers.S
View file @ c40c88f8
......@@ -18,16 +18,21 @@
/*******************************************************************************
* Implementation defined ACTLR_EL3 bit definitions
******************************************************************************/
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
#define ACTLR_EL3_L2ACTLR_BIT (U(1) << 6)
#define ACTLR_EL3_L2ECTLR_BIT (U(1) << 5)
#define ACTLR_EL3_L2CTLR_BIT (U(1) << 4)
#define ACTLR_EL3_CPUECTLR_BIT (U(1) << 1)
#define ACTLR_EL3_CPUACTLR_BIT (U(1) << 0)
#define ACTLR_EL3_ENABLE_ALL_MASK (ACTLR_EL3_L2ACTLR_BIT | \
ACTLR_EL3_L2ECTLR_BIT | \
ACTLR_EL3_L2CTLR_BIT | \
ACTLR_EL3_CPUECTLR_BIT | \
ACTLR_EL3_CPUACTLR_BIT)
#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
ACTLR_EL3_L2ECTLR_BIT | \
ACTLR_EL3_L2CTLR_BIT | \
ACTLR_EL3_CPUECTLR_BIT | \
ACTLR_EL3_CPUACTLR_BIT)
ACTLR_EL3_L2ECTLR_BIT | \
ACTLR_EL3_L2CTLR_BIT | \
ACTLR_EL3_CPUECTLR_BIT | \
ACTLR_EL3_CPUACTLR_BIT)
/* Global functions */
.globl plat_is_my_cpu_primary
......@@ -87,8 +92,17 @@
* Enable L2 and CPU ECTLR RW access from non-secure world
* -------------------------------------------------------
*/
mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS
mrs x0, actlr_el3
mov x1, #ACTLR_EL3_ENABLE_ALL_MASK
bic x0, x0, x1
mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS
orr x0, x0, x1
msr actlr_el3, x0
mrs x0, actlr_el2
mov x1, #ACTLR_EL3_ENABLE_ALL_MASK
bic x0, x0, x1
mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS
orr x0, x0, x1
msr actlr_el2, x0
isb
......@@ -130,17 +144,20 @@ func plat_is_my_cpu_primary
ret
endfunc plat_is_my_cpu_primary
/* -----------------------------------------------------
/* ----------------------------------------------------------
* unsigned int plat_my_core_pos(void);
*
* result: CorePos = CoreId + (ClusterId << 2)
* -----------------------------------------------------
* result: CorePos = CoreId + (ClusterId * cpus per cluster)
* ----------------------------------------------------------
*/
func plat_my_core_pos
mrs x0, mpidr_el1
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
add x0, x1, x0, LSR #6
lsr x0, x0, #MPIDR_AFFINITY_BITS
mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER
mul x0, x0, x2
add x0, x1, x0
ret
endfunc plat_my_core_pos
......@@ -162,14 +179,17 @@ endfunc plat_get_my_entrypoint
/* -----------------------------------------------------
* int platform_get_core_pos(int mpidr);
*
* With this function: CorePos = (ClusterId * 4) +
* CoreId
* result: CorePos = (ClusterId * cpus per cluster) +
* CoreId
* -----------------------------------------------------
*/
func platform_get_core_pos
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
add x0, x1, x0, LSR #6
lsr x0, x0, #MPIDR_AFFINITY_BITS
mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER
mul x0, x0, x2
add x0, x1, x0
ret
endfunc platform_get_core_pos
......@@ -400,31 +420,6 @@ restore_oslock:
mov x0, #1
msr oslar_el1, x0
cpu_init_common
/* ---------------------------------------------------------------------
* The initial state of the Architectural feature trap register
* (CPTR_EL3) is unknown and it must be set to a known state. All
* feature traps are disabled. Some bits in this register are marked as
* Reserved and should not be modified.
*
* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
* access to trace functionality is not supported, this bit is RES0.
* CPTR_EL3.TFP: This causes instructions that access the registers
* associated with Floating Point and Advanced SIMD execution to trap
* to EL3 when executed from any exception level, unless trapped to EL1
* or EL2.
* ---------------------------------------------------------------------
*/
mrs x1, cptr_el3
bic w1, w1, #TCPAC_BIT
bic w1, w1, #TTA_BIT
bic w1, w1, #TFP_BIT
msr cptr_el3, x1
/* --------------------------------------------------
* Get secure world's entry point and jump to it
* --------------------------------------------------
......
plat/nvidia/tegra/common/drivers/bpmp/bpmp.c
View file @ c40c88f8
......@@ -16,7 +16,7 @@
#include <string.h>
#include <tegra_def.h>
#define BPMP_TIMEOUT_10US 10
#define BPMP_TIMEOUT 2
static uint32_t channel_base[NR_CHANNELS];
static uint32_t bpmp_init_state = BPMP_INIT_PENDING;
......@@ -58,15 +58,15 @@ int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
if (bpmp_init_state == BPMP_INIT_COMPLETE) {
/* loop until BPMP is free */
for (timeout = 0; timeout < BPMP_TIMEOUT_10US; timeout++) {
for (timeout = 0; timeout < BPMP_TIMEOUT; timeout++) {
if (master_free(ch) == true) {
break;
}
udelay(1);
mdelay(1);
}
if (timeout != BPMP_TIMEOUT_10US) {
if (timeout != BPMP_TIMEOUT) {
/* generate the command struct */
p->code = mrq;
......@@ -76,18 +76,18 @@ int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
/* signal command ready to the BPMP */
signal_slave(ch);
mmio_write_32(TEGRA_PRI_ICTLR_BASE + CPU_IEP_FIR_SET,
(1UL << INT_SHR_SEM_OUTBOX_FULL));
(1U << INT_SHR_SEM_OUTBOX_FULL));
/* loop until the command is executed */
for (timeout = 0; timeout < BPMP_TIMEOUT_10US; timeout++) {
for (timeout = 0; timeout < BPMP_TIMEOUT; timeout++) {
if (master_acked(ch) == true) {
break;
}
udelay(1);
mdelay(1);
}
if (timeout != BPMP_TIMEOUT_10US) {
if (timeout != BPMP_TIMEOUT) {
/* get the command response */
(void)memcpy(ib_data, (const void *)p->data,
......@@ -106,8 +106,8 @@ int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
ret = -EINVAL;
}
if (timeout == BPMP_TIMEOUT_10US) {
ERROR("Timed out waiting for bpmp's response");
if (timeout == BPMP_TIMEOUT) {
ERROR("Timed out waiting for bpmp's response\n");
}
return ret;
......@@ -154,7 +154,7 @@ int tegra_bpmp_init(void)
channel_base[ch] = mmio_read_32(base);
/* increment result register offset */
base += 4UL;
base += 4U;
}
/* mark state as "initialized" */
......
plat/nvidia/tegra/common/drivers/gpcdma/gpcdma.c 0 → 100644
View file @ c40c88f8
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <delay_timer.h>
#include <errno.h>
#include <gpcdma.h>
#include <mmio.h>
#include <platform_def.h>
#include <stdbool.h>
#include <tegra_def.h>
#include <utils_def.h>
/* DMA channel registers */
#define DMA_CH_CSR U(0x0)
#define DMA_CH_CSR_WEIGHT_SHIFT U(10)
#define DMA_CH_CSR_XFER_MODE_SHIFT U(21)
#define DMA_CH_CSR_DMA_MODE_MEM2MEM U(4)
#define DMA_CH_CSR_DMA_MODE_FIXEDPATTERN U(6)
#define DMA_CH_CSR_IRQ_MASK_ENABLE (U(1) << 15)
#define DMA_CH_CSR_RUN_ONCE (U(1) << 27)
#define DMA_CH_CSR_ENABLE (U(1) << 31)
#define DMA_CH_STAT U(0x4)
#define DMA_CH_STAT_BUSY (U(1) << 31)
#define DMA_CH_SRC_PTR U(0xC)
#define DMA_CH_DST_PTR U(0x10)
#define DMA_CH_HI_ADR_PTR U(0x14)
#define DMA_CH_HI_ADR_PTR_SRC_MASK U(0xFF)
#define DMA_CH_HI_ADR_PTR_DST_SHIFT U(16)
#define DMA_CH_HI_ADR_PTR_DST_MASK U(0xFF)
#define DMA_CH_MC_SEQ U(0x18)
#define DMA_CH_MC_SEQ_REQ_CNT_SHIFT U(25)
#define DMA_CH_MC_SEQ_REQ_CNT_VAL U(0x10)
#define DMA_CH_MC_SEQ_BURST_SHIFT U(23)
#define DMA_CH_MC_SEQ_BURST_16_WORDS U(0x3)
#define DMA_CH_WORD_COUNT U(0x20)
#define DMA_CH_FIXED_PATTERN U(0x34)
#define DMA_CH_TZ U(0x38)
#define DMA_CH_TZ_ACCESS_ENABLE U(0)
#define DMA_CH_TZ_ACCESS_DISABLE U(3)
#define MAX_TRANSFER_SIZE (1U*1024U*1024U*1024U) /* 1GB */
#define GPCDMA_TIMEOUT_MS U(100)
#define GPCDMA_RESET_BIT (U(1) << 1)
static bool init_done;
static void tegra_gpcdma_write32(uint32_t offset, uint32_t val)
{
mmio_write_32(TEGRA_GPCDMA_BASE + offset, val);
}
static uint32_t tegra_gpcdma_read32(uint32_t offset)
{
return mmio_read_32(TEGRA_GPCDMA_BASE + offset);
}
static void tegra_gpcdma_init(void)
{
/* assert reset for DMA engine */
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPCDMA_RST_SET_REG_OFFSET,
GPCDMA_RESET_BIT);
udelay(2);
/* de-assert reset for DMA engine */
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPCDMA_RST_CLR_REG_OFFSET,
GPCDMA_RESET_BIT);
}
static void tegra_gpcdma_memcpy_priv(uint64_t dst_addr, uint64_t src_addr,
uint32_t num_bytes, uint32_t mode)
{
uint32_t val, timeout = 0;
int32_t ret = 0;
/* sanity check byte count */
if ((num_bytes > MAX_TRANSFER_SIZE) || ((num_bytes & 0x3U) != U(0))) {
ret = -EINVAL;
}
/* initialise GPCDMA block */
if (!init_done) {
tegra_gpcdma_init();
init_done = true;
}
/* make sure channel isn't busy */
val = tegra_gpcdma_read32(DMA_CH_STAT);
if ((val & DMA_CH_STAT_BUSY) == DMA_CH_STAT_BUSY) {
ERROR("DMA channel is busy\n");
ret = -EBUSY;
}
if (ret == 0) {
/* disable any DMA transfers */
tegra_gpcdma_write32(DMA_CH_CSR, 0);
/* enable DMA access to TZDRAM */
tegra_gpcdma_write32(DMA_CH_TZ, DMA_CH_TZ_ACCESS_ENABLE);
/* configure MC sequencer */
val = (DMA_CH_MC_SEQ_REQ_CNT_VAL << DMA_CH_MC_SEQ_REQ_CNT_SHIFT) |
(DMA_CH_MC_SEQ_BURST_16_WORDS << DMA_CH_MC_SEQ_BURST_SHIFT);
tegra_gpcdma_write32(DMA_CH_MC_SEQ, val);
/* reset fixed pattern */
tegra_gpcdma_write32(DMA_CH_FIXED_PATTERN, 0);
/* populate src and dst address registers */
tegra_gpcdma_write32(DMA_CH_SRC_PTR, (uint32_t)src_addr);
tegra_gpcdma_write32(DMA_CH_DST_PTR, (uint32_t)dst_addr);
val = (uint32_t)((src_addr >> 32) & DMA_CH_HI_ADR_PTR_SRC_MASK);
val |= (uint32_t)(((dst_addr >> 32) & DMA_CH_HI_ADR_PTR_DST_MASK) <<
DMA_CH_HI_ADR_PTR_DST_SHIFT);
tegra_gpcdma_write32(DMA_CH_HI_ADR_PTR, val);
/* transfer size (in words) */
tegra_gpcdma_write32(DMA_CH_WORD_COUNT, ((num_bytes >> 2) - 1U));
/* populate value for CSR */
val = (mode << DMA_CH_CSR_XFER_MODE_SHIFT) |
DMA_CH_CSR_RUN_ONCE | (U(1) << DMA_CH_CSR_WEIGHT_SHIFT) |
DMA_CH_CSR_IRQ_MASK_ENABLE;
tegra_gpcdma_write32(DMA_CH_CSR, val);
/* enable transfer */
val = tegra_gpcdma_read32(DMA_CH_CSR);
val |= DMA_CH_CSR_ENABLE;
tegra_gpcdma_write32(DMA_CH_CSR, val);
/* wait till transfer completes */
do {
/* read the status */
val = tegra_gpcdma_read32(DMA_CH_STAT);
if ((val & DMA_CH_STAT_BUSY) != DMA_CH_STAT_BUSY) {
break;
}
mdelay(1);
timeout++;
} while (timeout < GPCDMA_TIMEOUT_MS);
/* flag timeout error */
if (timeout == GPCDMA_TIMEOUT_MS) {
ERROR("DMA transfer timed out\n");
}
dsbsy();
/* disable DMA access to TZDRAM */
tegra_gpcdma_write32(DMA_CH_TZ, DMA_CH_TZ_ACCESS_DISABLE);
isb();
}
}
/*******************************************************************************
* Memcpy using GPCDMA block (Mem2Mem copy)
******************************************************************************/
void tegra_gpcdma_memcpy(uint64_t dst_addr, uint64_t src_addr,
uint32_t num_bytes)
{
tegra_gpcdma_memcpy_priv(dst_addr, src_addr, num_bytes,
DMA_CH_CSR_DMA_MODE_MEM2MEM);
}
/*******************************************************************************
* Memset using GPCDMA block (Fixed pattern write)
******************************************************************************/
void tegra_gpcdma_zeromem(uint64_t dst_addr, uint32_t num_bytes)
{
tegra_gpcdma_memcpy_priv(dst_addr, 0, num_bytes,
DMA_CH_CSR_DMA_MODE_FIXEDPATTERN);
}
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
View file @ c40c88f8
......@@ -109,13 +109,16 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
unsigned long long non_overlap_area_size)
{
int ret;
/*
* Map the NS memory first, clean it and then unmap it.
*/
mmap_add_dynamic_region(non_overlap_area_start, /* PA */
ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
non_overlap_area_start, /* VA */
non_overlap_area_size, /* size */
MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
assert(ret == 0);
zeromem((void *)non_overlap_area_start, non_overlap_area_size);
flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
......@@ -206,3 +209,16 @@ void tegra_memctrl_disable_ahb_redirection(void)
/* lock the aperture registers */
tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES);
}
void tegra_memctrl_clear_pending_interrupts(void)
{
uint32_t mcerr;
/* check if there are any pending interrupts */
mcerr = mmio_read_32(TEGRA_MC_BASE + MC_INTSTATUS);
if (mcerr != (uint32_t)0U) { /* should not see error here */
WARN("MC_INTSTATUS = 0x%x (should be zero)\n", mcerr);
mmio_write_32((TEGRA_MC_BASE + MC_INTSTATUS), mcerr);
}
}
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
View file @ c40c88f8
......@@ -287,13 +287,13 @@ static void tegra_memctrl_reconfig_mss_clients(void)
static void tegra_memctrl_set_overrides(void)
{
tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
const mc_txn_override_cfg_t *mc_txn_override_cfgs;
uint32_t num_txn_override_cfgs;
uint32_t i, val;
/* Get the settings from the platform */
assert(plat_mc_settings);
assert(plat_mc_settings != NULL);
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
......@@ -302,24 +302,24 @@ static void tegra_memctrl_set_overrides(void)
*/
if ((tegra_chipid_is_t186()) &&
(!tegra_platform_is_silicon() ||
(tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1)))) {
(tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) {
/*
* GPU and NVENC settings for Tegra186 simulation and
* Silicon rev. A01
*/
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
......@@ -330,7 +330,7 @@ static void tegra_memctrl_set_overrides(void)
*/
for (i = 0; i < num_txn_override_cfgs; i++) {
val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
val | mc_txn_override_cfgs[i].cgid_tag);
}
......@@ -347,7 +347,7 @@ void tegra_memctrl_setup(void)
uint32_t num_streamid_override_regs;
const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
uint32_t num_streamid_sec_cfgs;
tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
uint32_t i;
INFO("Tegra Memory Controller (v2)\n");
......@@ -357,7 +357,7 @@ void tegra_memctrl_setup(void)
tegra_smmu_init();
#endif
/* Get the settings from the platform */
assert(plat_mc_settings);
assert(plat_mc_settings != NULL);
mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
......@@ -421,7 +421,7 @@ void tegra_memctrl_restore_settings(void)
tegra_memctrl_set_overrides();
/* video memory carveout region */
if (video_mem_base) {
if (video_mem_base != 0ULL) {
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
(uint32_t)video_mem_base);
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
......@@ -444,6 +444,8 @@ void tegra_memctrl_restore_settings(void)
*/
void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
{
uint32_t val;
/*
* Setup the Memory controller to allow only secure accesses to
* the TZDRAM carveout
......@@ -458,15 +460,20 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
* When TZ encryption enabled,
* We need setup TZDRAM before CPU to access TZ Carveout,
* otherwise CPU will fetch non-decrypted data.
* So save TZDRAM setting for retore by SC7 resume FW.
* So save TZDRAM setting for restore by SC7 resume FW.
* Scratch registers map:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
*/
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO,
tegra_mc_read_32(MC_SECURITY_CFG0_0));
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI,
tegra_mc_read_32(MC_SECURITY_CFG3_0));
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI,
tegra_mc_read_32(MC_SECURITY_CFG1_0));
val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK;
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI, val);
val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK;
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, val);
val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, val);
/*
* MCE propagates the security configuration values across the
......@@ -525,7 +532,7 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
* at all.
*/
val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
val &= ~MC_GSC_ENABLE_TZ_LOCK_BIT;
val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
......@@ -600,18 +607,21 @@ static void tegra_unlock_videomem_nonoverlap(void)
static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
unsigned long long non_overlap_area_size)
{
int ret;
/*
* Map the NS memory first, clean it and then unmap it.
*/
mmap_add_dynamic_region(non_overlap_area_start, /* PA */
ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
non_overlap_area_start, /* VA */
non_overlap_area_size, /* size */
MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
assert(ret == 0);
zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size);
flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
mmap_remove_dynamic_region(non_overlap_area_start,
(void)mmap_remove_dynamic_region(non_overlap_area_start,
non_overlap_area_size);
}
......@@ -658,17 +668,19 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
*/
INFO("Cleaning previous Video Memory Carveout\n");
if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) {
if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) {
tegra_clear_videomem(video_mem_base,
(uint64_t)video_mem_size_mb << 20);
(uint32_t)video_mem_size_mb << 20U);
} else {
if (video_mem_base < phys_base) {
non_overlap_area_size = phys_base - video_mem_base;
tegra_clear_videomem(video_mem_base, non_overlap_area_size);
tegra_clear_videomem(video_mem_base,
(uint32_t)non_overlap_area_size);
}
if (vmem_end_old > vmem_end_new) {
non_overlap_area_size = vmem_end_old - vmem_end_new;
tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
tegra_clear_videomem(vmem_end_new,
(uint32_t)non_overlap_area_size);
}
}
......@@ -700,3 +712,8 @@ void tegra_memctrl_disable_ahb_redirection(void)
{
; /* do nothing */
}
void tegra_memctrl_clear_pending_interrupts(void)
{
; /* do nothing */
}
plat/nvidia/tegra/common/drivers/smmu/smmu.c
View file @ c40c88f8
......@@ -19,47 +19,55 @@ extern void memcpy16(void *dest, const void *src, unsigned int length);
/* SMMU IDs currently supported by the driver */
enum {
TEGRA_SMMU0,
TEGRA_SMMU0 = 0U,
TEGRA_SMMU1,
TEGRA_SMMU2
};
static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
{
uint32_t ret = 0U;
#if defined(TEGRA_SMMU0_BASE)
if (smmu_id == TEGRA_SMMU0)
return mmio_read_32(TEGRA_SMMU0_BASE + off);
if (smmu_id == TEGRA_SMMU0) {
ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off);
}
#endif
#if defined(TEGRA_SMMU1_BASE)
if (smmu_id == TEGRA_SMMU1)
return mmio_read_32(TEGRA_SMMU1_BASE + off);
if (smmu_id == TEGRA_SMMU1) {
ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off);
}
#endif
#if defined(TEGRA_SMMU2_BASE)
if (smmu_id == TEGRA_SMMU2)
return mmio_read_32(TEGRA_SMMU2_BASE + off);
if (smmu_id == TEGRA_SMMU2) {
ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off);
}
#endif
return 0;
return ret;
}
static void tegra_smmu_write_32(uint32_t smmu_id,
uint32_t off, uint32_t val)
{
#if defined(TEGRA_SMMU0_BASE)
if (smmu_id == TEGRA_SMMU0)
mmio_write_32(TEGRA_SMMU0_BASE + off, val);
if (smmu_id == TEGRA_SMMU0) {
mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val);
}
#endif
#if defined(TEGRA_SMMU1_BASE)
if (smmu_id == TEGRA_SMMU1)
mmio_write_32(TEGRA_SMMU1_BASE + off, val);
if (smmu_id == TEGRA_SMMU1) {
mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val);
}
#endif
#if defined(TEGRA_SMMU2_BASE)
if (smmu_id == TEGRA_SMMU2)
mmio_write_32(TEGRA_SMMU2_BASE + off, val);
if (smmu_id == TEGRA_SMMU2) {
mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val);
}
#endif
}
......@@ -70,23 +78,23 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
{
uint32_t i, num_entries = 0;
smmu_regs_t *smmu_ctx_regs;
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t tzdram_base = params_from_bl2->tzdram_base;
uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
uint32_t reg_id1, pgshift, cb_size;
/* sanity check SMMU settings c*/
reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
cb_size = (2 << pgshift) * \
(1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
pgshift = ((reg_id1 & ID1_PAGESIZE) != 0U) ? 16U : 12U;
cb_size = ((uint32_t)2 << pgshift) * \
((uint32_t)1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1U));
assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
/* get SMMU context table */
smmu_ctx_regs = plat_get_smmu_ctx();
assert(smmu_ctx_regs);
assert(smmu_ctx_regs != NULL);
/*
* smmu_ctx_regs[0].val contains the size of the context table minus
......@@ -98,19 +106,21 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
}
/* panic if the sizes do not match */
if (num_entries != smmu_ctx_regs[0].val)
if (num_entries != smmu_ctx_regs[0].val) {
panic();
}
/* save SMMU register values */
for (i = 1; i < num_entries; i++)
for (i = 1U; i < num_entries; i++) {
smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
}
/* increment by 1 to take care of the last entry */
num_entries++;
/* Save SMMU config settings */
memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
(sizeof(smmu_regs_t) * num_entries));
(void)memcpy16((uint8_t *)smmu_ctx_addr, (uint8_t *)smmu_ctx_regs,
(sizeof(smmu_regs_t) * num_entries));
/* save the SMMU table address */
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,
......@@ -128,17 +138,18 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
void tegra_smmu_init(void)
{
uint32_t val, cb_idx, smmu_id, ctx_base;
uint32_t smmu_counter = plat_get_num_smmu_devices();
for (smmu_id = 0; smmu_id < NUM_SMMU_DEVICES; smmu_id++) {
for (smmu_id = 0U; smmu_id < smmu_counter; smmu_id++) {
/* Program the SMMU pagesize and reset CACHE_LOCK bit */
val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
val |= SMMU_GSR0_PGSIZE_64K;
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
/* reset CACHE LOCK bit for NS Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
/* disable TCU prefetch for all contexts */
......@@ -147,19 +158,19 @@ void tegra_smmu_init(void)
for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
val = tegra_smmu_read_32(smmu_id,
ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT;
tegra_smmu_write_32(smmu_id, ctx_base +
(SMMU_GSR0_PGSIZE_64K * cb_idx), val);
}
/* set CACHE LOCK bit for NS Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
/* set CACHE LOCK bit for S Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
}
}
plat/nvidia/tegra/common/lib/debug/profiler.c 0 → 100644
View file @ c40c88f8
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************
* The profiler stores the timestamps captured during cold boot to the shared
* memory for the non-secure world. The non-secure world driver parses the
* shared memory block and writes the contents to a file on the device, which
* can be later extracted for analysis.
*
* Profiler memory map
*
* TOP --------------------------- ---
* Trusted OS timestamps 3KB
* --------------------------- ---
* Trusted Firmware timestamps 1KB
* BASE --------------------------- ---
*
******************************************************************************/
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
#include <mmio.h>
#include <profiler.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <utils_def.h>
#include <xlat_tables_v2.h>
static uint64_t shmem_base_addr;
#define MAX_PROFILER_RECORDS U(16)
#define TAG_LEN_BYTES U(56)
/*******************************************************************************
* Profiler entry format
******************************************************************************/
typedef struct {
/* text explaining the timestamp location in code */
uint8_t tag[TAG_LEN_BYTES];
/* timestamp value */
uint64_t timestamp;
} profiler_rec_t;
static profiler_rec_t *head, *cur, *tail;
static uint32_t tmr;
static bool is_shmem_buf_mapped;
/*******************************************************************************
* Initialise the profiling library
******************************************************************************/
void boot_profiler_init(uint64_t shmem_base, uint32_t tmr_base)
{
uint64_t shmem_end_base;
assert(shmem_base != ULL(0));
assert(tmr_base != U(0));
/* store the buffer address */
shmem_base_addr = shmem_base;
/* calculate the base address of the last record */
shmem_end_base = shmem_base + (sizeof(profiler_rec_t) *
(MAX_PROFILER_RECORDS - U(1)));
/* calculate the head, tail and cur values */
head = (profiler_rec_t *)shmem_base;
tail = (profiler_rec_t *)shmem_end_base;
cur = head;
/* timer used to get the current timestamp */
tmr = tmr_base;
}
/*******************************************************************************
* Add tag and timestamp to profiler
******************************************************************************/
void boot_profiler_add_record(const char *str)
{
unsigned int len;
/* calculate the length of the tag */
if (((unsigned int)strlen(str) + U(1)) > TAG_LEN_BYTES) {
len = TAG_LEN_BYTES;
} else {
len = (unsigned int)strlen(str) + U(1);
}
if (head != NULL) {
/*
* The profiler runs with/without MMU enabled. Check
* if MMU is enabled and memmap the shmem buffer, in
* case it is.
*/
if ((!is_shmem_buf_mapped) &&
((read_sctlr_el3() & SCTLR_M_BIT) != U(0))) {
(void)mmap_add_dynamic_region(shmem_base_addr,
shmem_base_addr,
PROFILER_SIZE_BYTES,
(MT_NS | MT_RW | MT_EXECUTE_NEVER));
is_shmem_buf_mapped = true;
}
/* write the tag and timestamp to buffer */
(void)snprintf((char *)cur->tag, len, "%s", str);
cur->timestamp = mmio_read_32(tmr);
/* start from head if we reached the end */
if (cur == tail) {
cur = head;
} else {
cur++;
}
}
}
/*******************************************************************************
* Deinint the profiler
******************************************************************************/
void boot_profiler_deinit(void)
{
if (shmem_base_addr != ULL(0)) {
/* clean up resources */
cur = NULL;
head = NULL;
tail = NULL;
/* flush the shmem for it to be visible to the NS world */
flush_dcache_range(shmem_base_addr, PROFILER_SIZE_BYTES);
/* unmap the shmem buffer */
if (is_shmem_buf_mapped) {
(void)mmap_remove_dynamic_region(shmem_base_addr,
PROFILER_SIZE_BYTES);
}
}
}
plat/nvidia/tegra/common/tegra_bl31_setup.c
View file @ c40c88f8
......@@ -26,6 +26,7 @@
#include <plat/common/platform.h>
#include <memctrl.h>
#include <profiler.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
......@@ -40,20 +41,19 @@ extern void memcpy16(void *dest, const void *src, unsigned int length);
* of trusted SRAM
******************************************************************************/
IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE);
IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END);
IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START);
IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END);
IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END);
IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE);
IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END);
IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START);
IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END);
extern uint64_t tegra_bl31_phys_base;
extern uint64_t tegra_console_base;
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
.tzdram_size = (uint64_t)TZDRAM_SIZE
.tzdram_size = TZDRAM_SIZE
};
static unsigned long bl32_mem_size;
static unsigned long bl32_boot_params;
......@@ -93,14 +93,16 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
******************************************************************************/
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
if (type == NON_SECURE)
return &bl33_image_ep_info;
entry_point_info_t *ep = NULL;
/* return BL32 entry point info if it is valid */
if (type == SECURE && bl32_image_ep_info.pc)
return &bl32_image_ep_info;
if (type == NON_SECURE) {
ep = &bl33_image_ep_info;
} else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
ep = &bl32_image_ep_info;
}
return NULL;
return ep;
}
/*******************************************************************************
......@@ -124,6 +126,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
image_info_t bl32_img_info = { {0} };
uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
uint32_t console_clock;
int32_t ret;
/*
* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
......@@ -131,20 +134,22 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
* might use custom ways to get arguments, so provide handlers which
* they can override.
*/
if (arg_from_bl2 == NULL)
if (arg_from_bl2 == NULL) {
arg_from_bl2 = plat_get_bl31_params();
if (plat_params == NULL)
}
if (plat_params == NULL) {
plat_params = plat_get_bl31_plat_params();
}
/*
* Copy BL3-3, BL3-2 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
assert(arg_from_bl2);
assert(arg_from_bl2->bl33_ep_info);
assert(arg_from_bl2 != NULL);
assert(arg_from_bl2->bl33_ep_info != NULL);
bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
if (arg_from_bl2->bl32_ep_info) {
if (arg_from_bl2->bl32_ep_info != NULL) {
bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
......@@ -153,7 +158,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/*
* Parse platform specific parameters - TZDRAM aperture base and size
*/
assert(plat_params);
assert(plat_params != NULL);
plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
......@@ -163,14 +168,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
* It is very important that we run either from TZDRAM or TZSRAM base.
* Add an explicit check here.
*/
if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) &&
(TEGRA_TZRAM_BASE != BL31_BASE))
if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
(TEGRA_TZRAM_BASE != BL31_BASE)) {
panic();
}
/*
* Reference clock used by the FPGAs is a lot slower.
*/
if (tegra_platform_is_fpga() == 1U) {
if (tegra_platform_is_fpga()) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
......@@ -182,14 +188,40 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
*/
tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
if (tegra_console_base != (uint64_t)0) {
if (tegra_console_base != 0U) {
/*
* Configure the UART port to be used as the console
*/
console_init(tegra_console_base, console_clock,
(void)console_init(tegra_console_base, console_clock,
TEGRA_CONSOLE_BAUDRATE);
}
/*
* The previous bootloader passes the base address of the shared memory
* location to store the boot profiler logs. Sanity check the
* address and initilise the profiler library, if it looks ok.
*/
if (plat_params->boot_profiler_shmem_base != 0ULL) {
ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
PROFILER_SIZE_BYTES);
if (ret == (int32_t)0) {
/* store the membase for the profiler lib */
plat_bl31_params_from_bl2.boot_profiler_shmem_base =
plat_params->boot_profiler_shmem_base;
/* initialise the profiler library */
boot_profiler_init(plat_params->boot_profiler_shmem_base,
TEGRA_TMRUS_BASE);
}
}
/*
* Add timestamp for platform early setup entry.
*/
boot_profiler_add_record("[TF] early setup entry");
/*
* Initialize delay timer
*/
......@@ -199,14 +231,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
* Do initial security configuration to allow DRAM/device access.
*/
tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
plat_bl31_params_from_bl2.tzdram_size);
(uint32_t)plat_bl31_params_from_bl2.tzdram_size);
/*
* The previous bootloader might not have placed the BL32 image
* inside the TZDRAM. We check the BL32 image info to find out
* the base/PC values and relocate the image if necessary.
*/
if (arg_from_bl2->bl32_image_info) {
if (arg_from_bl2->bl32_image_info != NULL) {
bl32_img_info = *arg_from_bl2->bl32_image_info;
......@@ -223,11 +255,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
assert(bl32_image_ep_info.pc < tzdram_end);
/* relocate BL32 */
if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) {
if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
INFO("Relocate BL32 to TZDRAM\n");
memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
(void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
(void *)(uintptr_t)bl32_start,
bl32_img_info.image_size);
......@@ -240,6 +272,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/* Early platform setup for Tegra SoCs */
plat_early_platform_setup();
/*
* Add timestamp for platform early setup exit.
*/
boot_profiler_add_record("[TF] early setup exit");
INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
(((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
== DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
......@@ -256,6 +293,9 @@ void plat_trusty_set_boot_args(aapcs64_params_t *args)
if (args->arg4 != 0U) {
args->arg2 = args->arg4;
}
/* Profiler Carveout Base */
args->arg3 = args->arg5;
}
#endif
......@@ -264,7 +304,10 @@ void plat_trusty_set_boot_args(aapcs64_params_t *args)
******************************************************************************/
void bl31_platform_setup(void)
{
uint32_t tmp_reg;
/*
* Add timestamp for platform setup entry.
*/
boot_profiler_add_record("[TF] plat setup entry");
/* Initialize the gic cpu and distributor interfaces */
plat_gic_setup();
......@@ -285,9 +328,10 @@ void bl31_platform_setup(void)
*/
tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
/* Set the next EL to be AArch64 */
tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
write_scr(tmp_reg);
/*
* Add timestamp for platform setup exit.
*/
boot_profiler_add_record("[TF] plat setup exit");
INFO("BL3-1: Tegra platform setup complete\n");
}
......@@ -297,6 +341,15 @@ void bl31_platform_setup(void)
******************************************************************************/
void bl31_plat_runtime_setup(void)
{
/*
* During cold boot, it is observed that the arbitration
* bit is set in the Memory controller leading to false
* error interrupts in the non-secure world. To avoid
* this, clean the interrupt status register before
* booting into the non-secure world
*/
tegra_memctrl_clear_pending_interrupts();
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need
* access to IRAM. Because these clients connect to the MC and
......@@ -307,6 +360,12 @@ void bl31_plat_runtime_setup(void)
* disabled before we jump to the non-secure world.
*/
tegra_memctrl_disable_ahb_redirection();
/*
* Add final timestamp before exiting BL31.
*/
boot_profiler_add_record("[TF] bl31 exit");
boot_profiler_deinit();
}
/*******************************************************************************
......@@ -315,17 +374,22 @@ void bl31_plat_runtime_setup(void)
******************************************************************************/
void bl31_plat_arch_setup(void)
{
unsigned long rw_start = BL31_RW_START;
unsigned long rw_size = BL31_RW_END - BL31_RW_START;
unsigned long rodata_start = BL31_RODATA_BASE;
unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
unsigned long code_base = TEXT_START;
unsigned long code_size = TEXT_END - TEXT_START;
uint64_t rw_start = BL31_RW_START;
uint64_t rw_size = BL31_RW_END - BL31_RW_START;
uint64_t rodata_start = BL31_RODATA_BASE;
uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
uint64_t code_base = TEXT_START;
uint64_t code_size = TEXT_END - TEXT_START;
const mmap_region_t *plat_mmio_map = NULL;
#if USE_COHERENT_MEM
unsigned long coh_start, coh_size;
uint32_t coh_start, coh_size;
#endif
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
/*
* Add timestamp for arch setup entry.
*/
boot_profiler_add_record("[TF] arch setup entry");
/* add memory regions */
mmap_add_region(rw_start, rw_start,
......@@ -352,21 +416,22 @@ void bl31_plat_arch_setup(void)
mmap_add_region(coh_start, coh_start,
coh_size,
MT_DEVICE | MT_RW | MT_SECURE);
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
#endif
/* map on-chip free running uS timer */
mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
(uint64_t)TEGRA_TMRUS_SIZE,
MT_DEVICE | MT_RO | MT_SECURE);
mmap_add_region(page_align(TEGRA_TMRUS_BASE, 0),
page_align(TEGRA_TMRUS_BASE, 0),
TEGRA_TMRUS_SIZE,
(uint8_t)MT_DEVICE | (uint8_t)MT_RO | (uint8_t)MT_SECURE);
/* add MMIO space */
plat_mmio_map = plat_get_mmio_map();
if (plat_mmio_map)
if (plat_mmio_map != NULL) {
mmap_add(plat_mmio_map);
else
} else {
WARN("MMIO map not available\n");
}
/* set up translation tables */
init_xlat_tables();
......@@ -374,33 +439,41 @@ void bl31_plat_arch_setup(void)
/* enable the MMU */
enable_mmu_el3(0);
/*
* Add timestamp for arch setup exit.
*/
boot_profiler_add_record("[TF] arch setup exit");
INFO("BL3-1: Tegra: MMU enabled\n");
}
/*******************************************************************************
* Check if the given NS DRAM range is valid
******************************************************************************/
int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
{
uint64_t end = base + size_in_bytes;
uint64_t end = base + size_in_bytes - U(1);
int32_t ret = 0;
/*
* Check if the NS DRAM address is valid
*/
if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) {
if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
(end > TEGRA_DRAM_END)) {
ERROR("NS address is out-of-bounds!\n");
return -EFAULT;
ret = -EFAULT;
}
/*
* TZDRAM aperture contains the BL31 and BL32 images, so we need
* to check if the NS DRAM range overlaps the TZDRAM aperture.
*/
if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
ERROR("NS address overlaps TZDRAM!\n");
return -ENOTSUP;
ret = -ENOTSUP;
}
/* valid NS address */
return 0;
return ret;
}
plat/nvidia/tegra/common/tegra_common.mk
View file @ c40c88f8
......@@ -5,6 +5,7 @@
#
PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \
-Iplat/nvidia/tegra/include/lib \
-Iplat/nvidia/tegra/include \
-Iplat/nvidia/tegra/include/${TARGET_SOC}
......@@ -25,6 +26,7 @@ BL31_SOURCES += drivers/console/aarch64/console.S \
${TEGRA_GICv2_SOURCES} \
${COMMON_DIR}/aarch64/tegra_helpers.S \
${COMMON_DIR}/drivers/pmc/pmc.c \
${COMMON_DIR}/lib/debug/profiler.c \
${COMMON_DIR}/tegra_bl31_setup.c \
${COMMON_DIR}/tegra_delay_timer.c \
${COMMON_DIR}/tegra_fiq_glue.c \
......
plat/nvidia/tegra/common/tegra_fiq_glue.c
View file @ c40c88f8
......@@ -65,7 +65,7 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
* Set the new ELR to continue execution in the NS world using the
* FIQ handler registered earlier.
*/
assert(ns_fiq_handler_addr);
assert(ns_fiq_handler_addr != 0ULL);
write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr));
/*
......
plat/nvidia/tegra/common/tegra_platform.c
View file @ c40c88f8
......@@ -15,7 +15,7 @@
* Tegra platforms
******************************************************************************/
typedef enum tegra_platform {
TEGRA_PLATFORM_SILICON = 0,
TEGRA_PLATFORM_SILICON = 0U,
TEGRA_PLATFORM_QT,
TEGRA_PLATFORM_FPGA,
TEGRA_PLATFORM_EMULATION,
......@@ -83,7 +83,7 @@ bool tegra_chipid_is_t132(void)
{
uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA13);
return (chip_id == TEGRA_CHIPID_TEGRA13);
}
bool tegra_chipid_is_t186(void)
......@@ -97,12 +97,12 @@ bool tegra_chipid_is_t210(void)
{
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA21);
return (chip_id == TEGRA_CHIPID_TEGRA21);
}
bool tegra_chipid_is_t210_b01(void)
{
return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2UL));
return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2U));
}
/*
......
plat/nvidia/tegra/common/tegra_pm.c
View file @ c40c88f8
......@@ -50,37 +50,42 @@ uint8_t tegra_fake_system_suspend;
#pragma weak tegra_soc_prepare_system_off
#pragma weak tegra_soc_get_target_pwr_state
int tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
{
return PSCI_E_NOT_SUPPORTED;
}
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{
(void)target_state;
return PSCI_E_NOT_SUPPORTED;
}
int tegra_soc_pwr_domain_on(u_register_t mpidr)
int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
{
(void)mpidr;
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
(void)target_state;
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
(void)target_state;
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
{
(void)target_state;
return PSCI_E_SUCCESS;
}
int tegra_soc_prepare_system_reset(void)
int32_t tegra_soc_prepare_system_reset(void)
{
return PSCI_E_SUCCESS;
}
......@@ -91,19 +96,26 @@ __dead2 void tegra_soc_prepare_system_off(void)
panic();
}
plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
const plat_local_state_t *states,
unsigned int ncpu)
uint32_t ncpu)
{
plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
uint32_t num_cpu = ncpu;
const plat_local_state_t *local_state = states;
(void)lvl;
assert(ncpu);
assert(ncpu != 0U);
do {
temp = *states++;
if ((temp < target))
temp = *local_state;
if ((temp < target)) {
target = temp;
} while (--ncpu);
}
--num_cpu;
local_state++;
} while (num_cpu != 0U);
return target;
}
......@@ -117,8 +129,9 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
/* all affinities use system suspend state id */
for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) {
req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
}
}
/*******************************************************************************
......@@ -126,6 +139,8 @@ void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
******************************************************************************/
void tegra_cpu_standby(plat_local_state_t cpu_state)
{
(void)cpu_state;
/*
* Enter standby state
* dsb is good practice before using wfi to enter low power states
......@@ -138,7 +153,7 @@ void tegra_cpu_standby(plat_local_state_t cpu_state)
* Handler called when an affinity instance is about to be turned on. The
* level and mpidr determine the affinity instance.
******************************************************************************/
int tegra_pwr_domain_on(u_register_t mpidr)
int32_t tegra_pwr_domain_on(u_register_t mpidr)
{
return tegra_soc_pwr_domain_on(mpidr);
}
......@@ -149,7 +164,7 @@ int tegra_pwr_domain_on(u_register_t mpidr)
******************************************************************************/
void tegra_pwr_domain_off(const psci_power_state_t *target_state)
{
tegra_soc_pwr_domain_off(target_state);
(void)tegra_soc_pwr_domain_off(target_state);
}
/*******************************************************************************
......@@ -169,12 +184,13 @@ void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_sta
******************************************************************************/
void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
{
tegra_soc_pwr_domain_suspend(target_state);
(void)tegra_soc_pwr_domain_suspend(target_state);
/* Disable console if we are entering deep sleep. */
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PSTATE_ID_SOC_POWERDN)
console_uninit();
PSTATE_ID_SOC_POWERDN) {
(void)console_uninit();
}
/* disable GICC */
tegra_gic_cpuif_deactivate();
......@@ -191,7 +207,7 @@ __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
uint64_t rmr_el3 = 0;
/* call the chip's power down handler */
tegra_soc_pwr_domain_power_down_wfi(target_state);
(void)tegra_soc_pwr_domain_power_down_wfi(target_state);
/*
* If we are in fake system suspend mode, ensure we start doing
......@@ -222,7 +238,7 @@ __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
******************************************************************************/
void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
plat_params_from_bl2_t *plat_params;
const plat_params_from_bl2_t *plat_params;
uint32_t console_clock;
/*
......@@ -239,15 +255,15 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
/*
* Reference clock used by the FPGAs is a lot slower.
*/
if (tegra_platform_is_fpga() == 1U) {
if (tegra_platform_is_fpga()) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
}
/* Initialize the runtime console */
if (tegra_console_base != (uint64_t)0) {
console_init(tegra_console_base, console_clock,
if (tegra_console_base != 0ULL) {
(void)console_init(tegra_console_base, console_clock,
TEGRA_CONSOLE_BAUDRATE);
}
......@@ -262,7 +278,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
*/
plat_params = bl31_get_plat_params();
tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
plat_params->tzdram_size);
(uint32_t)plat_params->tzdram_size);
/*
* Set up the TZRAM memory aperture to allow only secure world
......@@ -274,7 +290,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
/*
* Reset hardware settings.
*/
tegra_soc_pwr_domain_on_finish(target_state);
(void)tegra_soc_pwr_domain_on_finish(target_state);
}
/*******************************************************************************
......@@ -305,7 +321,7 @@ __dead2 void tegra_system_reset(void)
INFO("Restarting system...\n");
/* per-SoC system reset handler */
tegra_soc_prepare_system_reset();
(void)tegra_soc_prepare_system_reset();
/*
* Program the PMC in order to restart the system.
......@@ -316,10 +332,10 @@ __dead2 void tegra_system_reset(void)
/*******************************************************************************
* Handler called to check the validity of the power state parameter.
******************************************************************************/
int32_t tegra_validate_power_state(unsigned int power_state,
int32_t tegra_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state)
{
assert(req_state);
assert(req_state != NULL);
return tegra_soc_validate_power_state(power_state, req_state);
}
......@@ -327,16 +343,19 @@ int32_t tegra_validate_power_state(unsigned int power_state,
/*******************************************************************************
* Platform handler called to check the validity of the non secure entrypoint.
******************************************************************************/
int tegra_validate_ns_entrypoint(uintptr_t entrypoint)
int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint)
{
int32_t ret = PSCI_E_INVALID_ADDRESS;
/*
* Check if the non secure entrypoint lies within the non
* secure DRAM.
*/
if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END))
return PSCI_E_SUCCESS;
if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) {
ret = PSCI_E_SUCCESS;
}
return PSCI_E_INVALID_ADDRESS;
return ret;
}
/*******************************************************************************
......@@ -376,7 +395,7 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
/*
* Reset hardware settings.
*/
tegra_soc_pwr_domain_on_finish(&target_state);
(void)tegra_soc_pwr_domain_on_finish(&target_state);
/*
* Initialize PSCI ops struct
......
plat/nvidia/tegra/common/tegra_sip_calls.c
View file @ c40c88f8
......@@ -69,7 +69,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
void *handle,
u_register_t flags)
{
uint32_t regval;
uint32_t regval, local_x2_32 = (uint32_t)x2;
int32_t err;
/* Check if this is a SoC specific SiP */
......@@ -84,14 +84,11 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
/* clean up the high bits */
x2 = (uint32_t)x2;
/*
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
* or falls outside of the valid DRAM range
*/
err = bl31_check_ns_address(x1, x2);
err = bl31_check_ns_address(x1, local_x2_32);
if (err != 0) {
SMC_RET1(handle, (uint64_t)err);
}
......@@ -99,9 +96,9 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
/*
* Check if Video Memory is aligned to 1MB.
*/
if (((x1 & 0xFFFFFU) != 0U) || ((x2 & 0xFFFFFU) != 0U)) {
if (((x1 & 0xFFFFFU) != 0U) || ((local_x2_32 & 0xFFFFFU) != 0U)) {
ERROR("Unaligned Video Memory base address!\n");
SMC_RET1(handle, -ENOTSUP);
SMC_RET1(handle, (uint64_t)-ENOTSUP);
}
/*
......@@ -111,13 +108,13 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
*/
regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
TEGRA_GPU_RESET_REG_OFFSET);
if ((regval & GPU_RESET_BIT) == 0UL) {
if ((regval & GPU_RESET_BIT) == 0U) {
ERROR("GPU not in reset! Video Memory setup failed\n");
SMC_RET1(handle, -ENOTSUP);
SMC_RET1(handle, (uint64_t)-ENOTSUP);
}
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, (uint32_t)x2);
tegra_memctrl_videomem_setup(x1, local_x2_32);
SMC_RET1(handle, 0);
......
plat/nvidia/tegra/common/tegra_topology.c
View file @ c40c88f8
......@@ -23,10 +23,14 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
u_register_t cluster_id, cpu_id;
int32_t result;
cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
result = (int32_t)cpu_id + ((int32_t)cluster_id * 4);
cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) &
(u_register_t)MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) &
(u_register_t)MPIDR_AFFLVL_MASK;
/* CorePos = CoreId + (ClusterId * cpus per cluster) */
result = (int32_t)cpu_id + ((int32_t)cluster_id *
PLATFORM_MAX_CPUS_PER_CLUSTER);
if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) {
result = PSCI_E_NOT_PRESENT;
......
plat/nvidia/tegra/include/drivers/bpmp.h
View file @ c40c88f8
......@@ -10,25 +10,25 @@
#include <stdint.h>
/* macro to enable clock to the Atomics block */
#define CAR_ENABLE_ATOMICS (1UL << 16)
#define CAR_ENABLE_ATOMICS (1U << 16)
/* command to get the channel base addresses from bpmp */
#define ATOMIC_CMD_GET 4UL
#define ATOMIC_CMD_GET 4U
/* Hardware IRQ # used to signal bpmp of an incoming command */
#define INT_SHR_SEM_OUTBOX_FULL 6UL
#define INT_SHR_SEM_OUTBOX_FULL 6U
/* macros to decode the bpmp's state */
#define CH_MASK(ch) (0x3UL << ((ch) * 2UL))
#define MA_FREE(ch) (0x2UL << ((ch) * 2UL))
#define MA_ACKD(ch) (0x3UL << ((ch) * 2UL))
#define CH_MASK(ch) ((uint32_t)0x3 << ((ch) * 2U))
#define MA_FREE(ch) ((uint32_t)0x2 << ((ch) * 2U))
#define MA_ACKD(ch) ((uint32_t)0x3 << ((ch) * 2U))
/* response from bpmp to indicate it has powered up */
#define SIGN_OF_LIFE 0xAAAAAAAAUL
#define SIGN_OF_LIFE 0xAAAAAAAAU
/* flags to indicate bpmp driver's state */
#define BPMP_INIT_COMPLETE 0xBEEFF00DUL
#define BPMP_INIT_PENDING 0xDEADBEEFUL
#define BPMP_INIT_COMPLETE 0xBEEFF00DU
#define BPMP_INIT_PENDING 0xDEADBEEFU
/* requests serviced by the bpmp */
#define MRQ_PING 0
......@@ -64,14 +64,14 @@
#define TEGRA_PM_SC7 23
/* flag to indicate if entry into a CCx power state is allowed */
#define BPMP_CCx_ALLOWED 0UL
#define BPMP_CCx_ALLOWED 0U
/* number of communication channels to interact with the bpmp */
#define NR_CHANNELS 4U
/* flag to ask bpmp to acknowledge command packet */
#define NO_ACK (0UL << 0UL)
#define DO_ACK (1UL << 0UL)
#define NO_ACK (0U << 0U)
#define DO_ACK (1U << 0U)
/* size of the command/response data */
#define MSG_DATA_MAX_SZ 120U
......
plat/nvidia/tegra/include/drivers/gpcdma.h 0 → 100644
View file @ c40c88f8
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __GPCDMA_H__
#define __GPCDMA_H__
#include <stdint.h>
void tegra_gpcdma_memcpy(uint64_t dst_addr, uint64_t src_addr,
uint32_t num_bytes);
void tegra_gpcdma_zeromem(uint64_t dst_addr, uint32_t num_bytes);
#endif /* __GPCDMA_H__ */
plat/nvidia/tegra/include/drivers/memctrl.h
View file @ c40c88f8
......@@ -13,5 +13,6 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_disable_ahb_redirection(void);
void tegra_memctrl_clear_pending_interrupts(void);
#endif /* MEMCTRL_H */
plat/nvidia/tegra/include/drivers/security_engine.h
View file @ c40c88f8
......@@ -38,8 +38,16 @@ typedef struct tegra_se_dev {
tegra_se_io_lst_t *src_ll_buf;
/* pointer to destination linked list buffer */
tegra_se_io_lst_t *dst_ll_buf;
/* LP context buffer pointer */
uint32_t *ctx_save_buf;
} tegra_se_dev_t;
/* PKA1 device structure */
typedef struct tegra_pka_dev {
/* PKA1 base address */
uint64_t pka_base;
} tegra_pka_dev_t;
/*******************************************************************************
* Public interface
******************************************************************************/
......
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