Merge pull request #1263 from soby-mathew/sm/dyn_config

Dynamic Configuration Prototype

Makefile

@@ -125,7 +125,7 @@ OC			:=	${CROSS_COMPILE}objcopy
 OD			:=	${CROSS_COMPILE}objdump
 NM			:=	${CROSS_COMPILE}nm
 PP			:=	${CROSS_COMPILE}gcc -E
-DTC			?=	dtc
+DTC			:=	dtc
 
 # Use ${LD}.bfd instead if it exists (as absolute path or together with $PATH).
 ifneq ($(strip $(wildcard ${LD}.bfd) \
@@ -192,8 +192,8 @@ BL_COMMON_SOURCES	+=	common/bl_common.c			\
 				common/${ARCH}/debug.S			\
 				lib/${ARCH}/cache_helpers.S		\
 				lib/${ARCH}/misc_helpers.S		\
+				plat/common/plat_bl_common.c		\
 				plat/common/plat_log_common.c		\
-				plat/common/platform_helpers_default.c	\
 				plat/common/${ARCH}/plat_common.c	\
 				plat/common/${ARCH}/platform_helpers.S	\
 				${COMPILER_RT_SRCS}			\
@@ -638,9 +638,7 @@ endif
 
 # Expand build macros for the different images
 ifeq (${NEED_FDT},yes)
-$(eval $(call MAKE_DTBS,$(BUILD_PLAT)/fdts,$(FDT_SOURCES)))
-$(eval $(call MAKE_FDT))
-dtbs: $(DTBS)
+    $(eval $(call MAKE_DTBS,$(BUILD_PLAT)/fdts,$(FDT_SOURCES)))
 endif
 
 locate-checkpatch:
@@ -777,7 +775,7 @@ help:
 	@echo "  distclean      Remove all build artifacts for all platforms"
 	@echo "  certtool       Build the Certificate generation tool"
 	@echo "  fiptool        Build the Firmware Image Package (FIP) creation tool"
-	@echo "  dtbs           Build the Flattened device tree (if required for the platform)"
+	@echo "  dtbs           Build the Device Tree Blobs (if required for the platform)"
 	@echo ""
 	@echo "Note: most build targets require PLAT to be set to a specific platform."
 	@echo ""

bl1/bl1_fwu.c

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -350,6 +350,15 @@ static int bl1_fwu_image_copy(unsigned int image_id,
 		return -ENOMEM;
 	}
 
+	/* Allow the platform to handle pre-image load before copying */
+	if (image_desc->state == IMAGE_STATE_RESET) {
+		if (bl1_plat_handle_pre_image_load(image_id) != 0) {
+			ERROR("BL1-FWU: Failure in pre-image load of image id %d\n",
+					image_id);
+			return -EPERM;
+		}
+	}
+
 	/* Everything looks sane. Go ahead and copy the block of data. */
 	dest_addr = image_desc->image_info.image_base + image_desc->copied_size;
 	memcpy((void *) dest_addr, (const void *) image_src, block_size);
@@ -474,6 +483,18 @@ static int bl1_fwu_image_auth(unsigned int image_id,
 	/* Indicate that image is in authenticated state. */
 	image_desc->state = IMAGE_STATE_AUTHENTICATED;
 
+	/* Allow the platform to handle post-image load */
+	result = bl1_plat_handle_post_image_load(image_id);
+	if (result != 0) {
+		ERROR("BL1-FWU: Failure %d in post-image load of image id %d\n",
+				result, image_id);
+		/*
+		 * Panic here as the platform handling of post-image load is
+		 * not correct.
+		 */
+		plat_error_handler(result);
+	}
+
 	/*
 	 * Flush image_info to memory so that other
 	 * secure world images can see changes.

bl1/bl1_main.c

@@ -25,24 +25,15 @@ DEFINE_SVC_UUID(bl1_svc_uid,
 	0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75,
 	0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
 
-
 static void bl1_load_bl2(void);
 
 /*******************************************************************************
- * The next function has a weak definition. Platform specific code can override
- * it if it wishes to.
- ******************************************************************************/
-#pragma weak bl1_init_bl2_mem_layout
-
-/*******************************************************************************
- * Function that takes a memory layout into which BL2 has been loaded and
- * populates a new memory layout for BL2 that ensures that BL1's data sections
- * resident in secure RAM are not visible to BL2.
+ * Helper utility to calculate the BL2 memory layout taking into consideration
+ * the BL1 RW data assuming that it is at the top of the memory layout.
  ******************************************************************************/
-void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
-			     meminfo_t *bl2_mem_layout)
+void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
+			meminfo_t *bl2_mem_layout)
 {
-
 	assert(bl1_mem_layout != NULL);
 	assert(bl2_mem_layout != NULL);
 
@@ -71,6 +62,25 @@ void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
 	flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
 }
 
+#if !ERROR_DEPRECATED
+/*******************************************************************************
+ * Compatibility default implementation for deprecated API. This has a weak
+ * definition. Platform specific code can override it if it wishes to.
+ ******************************************************************************/
+#pragma weak bl1_init_bl2_mem_layout
+
+/*******************************************************************************
+ * Function that takes a memory layout into which BL2 has been loaded and
+ * populates a new memory layout for BL2 that ensures that BL1's data sections
+ * resident in secure RAM are not visible to BL2.
+ ******************************************************************************/
+void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
+			     meminfo_t *bl2_mem_layout)
+{
+	bl1_calc_bl2_mem_layout(bl1_mem_layout, bl2_mem_layout);
+}
+#endif
+
 /*******************************************************************************
  * Function to perform late architectural and platform specific initialization.
  * It also queries the platform to load and run next BL image. Only called
@@ -157,9 +167,6 @@ void bl1_load_bl2(void)
 {
 	image_desc_t *image_desc;
 	image_info_t *image_info;
-	entry_point_info_t *ep_info;
-	meminfo_t *bl1_tzram_layout;
-	meminfo_t *bl2_tzram_layout;
 	int err;
 
 	/* Get the image descriptor */
@@ -168,24 +175,26 @@ void bl1_load_bl2(void)
 
 	/* Get the image info */
 	image_info = &image_desc->image_info;
-
-	/* Get the entry point info */
-	ep_info = &image_desc->ep_info;
-
-	/* Find out how much free trusted ram remains after BL1 load */
-	bl1_tzram_layout = bl1_plat_sec_mem_layout();
-
 	INFO("BL1: Loading BL2\n");
 
-#if LOAD_IMAGE_V2
-	err = bl1_plat_handle_pre_image_load();
+	err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
 	if (err) {
 		ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
 		plat_error_handler(err);
 	}
 
+#if LOAD_IMAGE_V2
 	err = load_auth_image(BL2_IMAGE_ID, image_info);
 #else
+	entry_point_info_t *ep_info;
+	meminfo_t *bl1_tzram_layout;
+
+	/* Get the entry point info */
+	ep_info = &image_desc->ep_info;
+
+	/* Find out how much free trusted ram remains after BL1 load */
+	bl1_tzram_layout = bl1_plat_sec_mem_layout();
+
 	/* Load the BL2 image */
 	err = load_auth_image(bl1_tzram_layout,
 			 BL2_IMAGE_ID,
@@ -200,32 +209,14 @@ void bl1_load_bl2(void)
 		plat_error_handler(err);
 	}
 
-#if LOAD_IMAGE_V2
 	/* Allow platform to handle image information. */
-	err = bl1_plat_handle_post_image_load();
+	err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
 	if (err) {
 		ERROR("Failure in post image load handling of BL2 (%d)\n", err);
 		plat_error_handler(err);
 	}
 
-	/*
-	 * Create a new layout of memory for BL2 as seen by BL1 i.e.
-	 * tell it the amount of total and free memory available.
-	 * This layout is created at the first free address visible
-	 * to BL2. BL2 will read the memory layout before using its
-	 * memory for other purposes.
-	 */
-	bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base;
-#else
-	bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
-#endif /* LOAD_IMAGE_V2 */
-
-	bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
-
-	ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
 	NOTICE("BL1: Booting BL2\n");
-	VERBOSE("BL1: BL2 memory layout address = %p\n",
-		(void *) bl2_tzram_layout);
 }
 
 /*******************************************************************************

bl2/aarch32/bl2_entrypoint.S

 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,12 +26,14 @@ vector_base bl2_vector_table
 
 func bl2_entrypoint
 	/*---------------------------------------------
-	 * Save from r1 the extents of the trusted ram
-	 * available to BL2 for future use.
-	 * r0 is not currently used.
+	 * Save arguments x0 - x3 from BL1 for future
+	 * use.
 	 * ---------------------------------------------
 	 */
- 	mov	r11, r1
+	mov	r9, r0
+	mov	r10, r1
+	mov	r11, r2
+	mov	r12, r3
 
 	/* ---------------------------------------------
 	 * Set the exception vector to something sane.
@@ -111,8 +113,11 @@ func bl2_entrypoint
 	 * specific early arch. setup e.g. mmu setup
 	 * ---------------------------------------------
 	 */
-	mov	r0, r11
-	bl	bl2_early_platform_setup
+	mov	r0, r9
+	mov	r1, r10
+	mov	r2, r11
+	mov	r3, r12
+	bl	bl2_early_platform_setup2
 	bl	bl2_plat_arch_setup
 
 	/* ---------------------------------------------

bl2/aarch64/bl2_entrypoint.S

 /*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,12 +15,14 @@
 
 func bl2_entrypoint
 	/*---------------------------------------------
-	 * Save from x1 the extents of the tzram
-	 * available to BL2 for future use.
-	 * x0 is not currently used.
+	 * Save arguments x0 - x3 from BL1 for future
+	 * use.
 	 * ---------------------------------------------
 	 */
-	mov	x20, x1
+	mov	x20, x0
+	mov	x21, x1
+	mov	x22, x2
+	mov	x23, x3
 
 	/* ---------------------------------------------
 	 * Set the exception vector to something sane.
@@ -103,7 +105,11 @@ func bl2_entrypoint
 	 * ---------------------------------------------
 	 */
 	mov	x0, x20
-	bl	bl2_early_platform_setup
+	mov	x1, x21
+	mov	x2, x22
+	mov	x3, x23
+	bl	bl2_early_platform_setup2
+
 	bl	bl2_plat_arch_setup
 
 	/* ---------------------------------------------

bl2/bl2.mk

@@ -29,7 +29,6 @@ BL2_LINKERFILE		:=	bl2/bl2.ld.S
 else
 BL2_SOURCES		+=	bl2/${ARCH}/bl2_el3_entrypoint.S	\
 				bl2/${ARCH}/bl2_el3_exceptions.S	\
-				plat/common/plat_bl2_el3_common.c	\
 				lib/cpus/${ARCH}/cpu_helpers.S		\
 				lib/cpus/errata_report.c
 BL2_LINKERFILE		:=	bl2/bl2_el3.ld.S

bl31/aarch64/bl31_entrypoint.S

 /*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,13 +23,13 @@
 func bl31_entrypoint
 #if !RESET_TO_BL31
 	/* ---------------------------------------------------------------
-	 * Preceding bootloader has populated x0 with a pointer to a
-	 * 'bl31_params' structure & x1 with a pointer to platform
-	 * specific structure
+	 * Stash the previous bootloader arguments x0 - x3 for later use.
 	 * ---------------------------------------------------------------
 	 */
 	mov	x20, x0
 	mov	x21, x1
+	mov	x22, x2
+	mov	x23, x3
 
 	/* ---------------------------------------------------------------------
 	 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches
@@ -47,13 +47,6 @@ func bl31_entrypoint
 		_init_memory=0					\
 		_init_c_runtime=1				\
 		_exception_vectors=runtime_exceptions
-
-	/* ---------------------------------------------------------------------
-	 * Relay the previous bootloader's arguments to the platform layer
-	 * ---------------------------------------------------------------------
-	 */
-	mov	x0, x20
-	mov	x1, x21
 #else
 	/* ---------------------------------------------------------------------
 	 * For RESET_TO_BL31 systems which have a programmable reset address,
@@ -75,15 +68,20 @@ func bl31_entrypoint
 	 * arguments passed to the platform layer to reflect that.
 	 * ---------------------------------------------------------------------
 	 */
-	mov	x0, 0
-	mov	x1, 0
+	mov	x20, 0
+	mov	x21, 0
+	mov	x22, 0
+	mov	x23, 0
 #endif /* RESET_TO_BL31 */
-
 	/* ---------------------------------------------
 	 * Perform platform specific early arch. setup
 	 * ---------------------------------------------
 	 */
-	bl	bl31_early_platform_setup
+	mov	x0, x20
+	mov	x1, x21
+	mov	x2, x22
+	mov	x3, x23
+	bl	bl31_early_platform_setup2
 	bl	bl31_plat_arch_setup
 
 	/* ---------------------------------------------

bl32/sp_min/aarch32/entrypoint.S

@@ -64,8 +64,10 @@ func sp_min_entrypoint
 	 * specific structure
 	 * ---------------------------------------------------------------
 	 */
-	mov	r11, r0
-	mov	r12, r1
+	mov	r9, r0
+	mov	r10, r1
+	mov	r11, r2
+	mov	r12, r3
 
 	/* ---------------------------------------------------------------------
 	 * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
@@ -88,8 +90,6 @@ func sp_min_entrypoint
 	 * Relay the previous bootloader's arguments to the platform layer
 	 * ---------------------------------------------------------------------
 	 */
-	mov	r0, r11
-	mov	r1, r12
 #else
 	/* ---------------------------------------------------------------------
 	 * For RESET_TO_SP_MIN systems which have a programmable reset address,
@@ -111,15 +111,22 @@ func sp_min_entrypoint
 	 * Zero the arguments passed to the platform layer to reflect that.
 	 * ---------------------------------------------------------------------
 	 */
-	mov	r0, #0
-	mov	r1, #0
+	mov	r9, #0
+	mov	r10, #0
+	mov	r11, #0
+	mov	r12, #0
+
 #endif /* RESET_TO_SP_MIN */
 
 #if SP_MIN_WITH_SECURE_FIQ
 	route_fiq_to_sp_min r4
 #endif
 
-	bl	sp_min_early_platform_setup
+	mov	r0, r9
+	mov	r1, r10
+	mov	r2, r11
+	mov	r3, r12
+	bl	sp_min_early_platform_setup2
 	bl	sp_min_plat_arch_setup
 
 	/* Jump to the main function */

common/desc_image_load.c

@@ -190,3 +190,65 @@ bl_params_t *get_next_bl_params_from_mem_params_desc(void)
 
 	return &next_bl_params;
 }
+
+/*******************************************************************************
+ * This function populates the entry point information with the corresponding
+ * config file for all executable BL images described in bl_params.
+ ******************************************************************************/
+void populate_next_bl_params_config(bl_params_t *bl2_to_next_bl_params)
+{
+	bl_params_node_t *params_node;
+	unsigned int fw_config_id;
+	uintptr_t hw_config_base = 0, fw_config_base;
+	bl_mem_params_node_t *mem_params;
+
+	assert(bl2_to_next_bl_params != NULL);
+
+	/*
+	 * Get the `bl_mem_params_node_t` corresponding to HW_CONFIG
+	 * if available.
+	 */
+	mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
+	if (mem_params != NULL)
+		hw_config_base = mem_params->image_info.image_base;
+
+	for (params_node = bl2_to_next_bl_params->head; params_node != NULL;
+			params_node = params_node->next_params_info) {
+
+		fw_config_base = 0;
+
+		switch (params_node->image_id) {
+		case BL31_IMAGE_ID:
+			fw_config_id = SOC_FW_CONFIG_ID;
+			break;
+		case BL32_IMAGE_ID:
+			fw_config_id = TOS_FW_CONFIG_ID;
+			break;
+		case BL33_IMAGE_ID:
+			fw_config_id = NT_FW_CONFIG_ID;
+			break;
+		default:
+			fw_config_id = INVALID_IMAGE_ID;
+			break;
+		}
+
+		if (fw_config_id != INVALID_IMAGE_ID) {
+			mem_params = get_bl_mem_params_node(fw_config_id);
+			if (mem_params != NULL)
+				fw_config_base = mem_params->image_info.image_base;
+		}
+
+		/*
+		 * Pass hw and tb_fw config addresses to next images. NOTE - for
+		 * EL3 runtime images (BL31 for AArch64 and BL32 for AArch32),
+		 * arg0 is already used by generic code.
+		 */
+		if (params_node == bl2_to_next_bl_params->head) {
+			params_node->ep_info->args.arg1 = fw_config_base;
+			params_node->ep_info->args.arg2 = hw_config_base;
+		} else {
+			params_node->ep_info->args.arg0 = fw_config_base;
+			params_node->ep_info->args.arg1 = hw_config_base;
+		}
+	}
+}

common/fdt_wrappers.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Helper functions to offer easier navigation of Device Tree Blob */
+
+#include <assert.h>
+#include <debug.h>
+#include <fdt_wrappers.h>
+#include <libfdt.h>
+
+/*
+ * Read cells from a given property of the given node. At most 2 cells of the
+ * property are read, and pointer is updated. Returns 0 on success, and -1 upon
+ * error
+ */
+int fdtw_read_cells(const void *dtb, int node, const char *prop,
+		unsigned int cells, void *value)
+{
+	const uint32_t *value_ptr;
+	uint32_t hi = 0, lo;
+	int value_len;
+
+	assert(dtb != NULL);
+	assert(prop != NULL);
+	assert(value != NULL);
+	assert(node >= 0);
+
+	/* We expect either 1 or 2 cell property */
+	assert(cells <= 2U);
+
+	/* Access property and obtain its length (in bytes) */
+	value_ptr = fdt_getprop_namelen(dtb, node, prop, (int)strlen(prop),
+			&value_len);
+	if (value_ptr == NULL) {
+		WARN("Couldn't find property %s in dtb\n", prop);
+		return -1;
+	}
+
+
+	/* Verify that property length accords with cell length */
+	if (NCELLS((unsigned int)value_len) != cells) {
+		WARN("Property length mismatch\n");
+		return -1;
+	}
+
+	if (cells == 2U) {
+		hi = fdt32_to_cpu(*value_ptr);
+		value_ptr++;
+	}
+
+	lo = fdt32_to_cpu(*value_ptr);
+
+	if (cells == 2U)
+		*((uint64_t *) value) = ((uint64_t) hi << 32) | lo;
+	else
+		*((uint32_t *) value) = lo;
+
+	return 0;
+}
+
+/*
+ * Write cells in place to a given property of the given node. At most 2 cells
+ * of the property are written. Returns 0 on success, and -1 upon error.
+ */
+int fdtw_write_inplace_cells(void *dtb, int node, const char *prop,
+		unsigned int cells, void *value)
+{
+	int err, len;
+
+	assert(dtb != NULL);
+	assert(prop != NULL);
+	assert(value != NULL);
+	assert(node >= 0);
+
+	/* We expect either 1 or 2 cell property */
+	assert(cells <= 2U);
+
+	if (cells == 2U)
+		*(uint64_t *)value = cpu_to_fdt64(*(uint64_t *)value);
+	else
+		*(uint32_t *)value = cpu_to_fdt32(*(uint32_t *)value);
+
+	len = (int)cells * 4;
+
+	/* Set property value in place */
+	err = fdt_setprop_inplace(dtb, node, prop, value, len);
+	if (err != 0) {
+		WARN("Modify property %s failed with error %d\n", prop, err);
+		return -1;
+	}
+
+	return 0;
+}

docs/porting-guide.rst

@@ -1179,25 +1179,6 @@ its own use.
 
 This function helps fulfill requirements 4 and 5 above.
 
-Function : bl1\_init\_bl2\_mem\_layout() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
-    Argument : meminfo *, meminfo *
-    Return   : void
-
-BL1 needs to tell the next stage the amount of secure RAM available
-for it to use. This information is populated in a ``meminfo``
-structure.
-
-Depending upon where BL2 has been loaded in secure RAM (determined by
-``BL2_BASE``), BL1 calculates the amount of free memory available for BL2 to use.
-BL1 also ensures that its data sections resident in secure RAM are not visible
-to BL2. An illustration of how this is done in ARM standard platforms is given
-in the **Memory layout on ARM development platforms** section in the
-`Firmware Design`_.
-
 Function : bl1\_plat\_prepare\_exit() [optional]
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -1264,24 +1245,24 @@ Function : bl1\_plat\_handle\_pre\_image\_load() [optional]
 
 ::
 
-    Argument : void
+    Argument : unsigned int image_id
     Return   : int
 
 This function can be used by the platforms to update/use image information
-for BL2. This function is currently invoked in BL1 before loading BL2,
-when LOAD\_IMAGE\_V2 is enabled.
+corresponding to ``image_id``. This function is invoked in BL1, both in cold
+boot and FWU code path, before loading the image.
 
 Function : bl1\_plat\_handle\_post\_image\_load() [optional]
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 ::
 
-    Argument : void
+    Argument : unsigned int image_id
     Return   : int
 
 This function can be used by the platforms to update/use image information
-for BL2. This function is currently invoked in BL1 after loading BL2,
-when LOAD\_IMAGE\_V2 is enabled.
+corresponding to ``image_id``. This function is invoked in BL1, both in cold
+boot and FWU code path, after loading and authenticating the image.
 
 Function : bl1\_plat\_fwu\_done() [optional]
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

drivers/auth/tbbr/tbbr_cot.c

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,6 +27,8 @@
  * established, we can reuse some of the buffers on different stages
  */
 static unsigned char tb_fw_hash_buf[HASH_DER_LEN];
+static unsigned char tb_fw_config_hash_buf[HASH_DER_LEN];
+static unsigned char hw_config_hash_buf[HASH_DER_LEN];
 static unsigned char scp_fw_hash_buf[HASH_DER_LEN];
 static unsigned char soc_fw_hash_buf[HASH_DER_LEN];
 static unsigned char tos_fw_hash_buf[HASH_DER_LEN];
@@ -70,6 +72,10 @@ static auth_param_type_desc_t nt_fw_content_pk = AUTH_PARAM_TYPE_DESC(
 
 static auth_param_type_desc_t tb_fw_hash = AUTH_PARAM_TYPE_DESC(
 		AUTH_PARAM_HASH, TRUSTED_BOOT_FW_HASH_OID);
+static auth_param_type_desc_t tb_fw_config_hash = AUTH_PARAM_TYPE_DESC(
+		AUTH_PARAM_HASH, TRUSTED_BOOT_FW_CONFIG_HASH_OID);
+static auth_param_type_desc_t hw_config_hash = AUTH_PARAM_TYPE_DESC(
+		AUTH_PARAM_HASH, HW_CONFIG_HASH_OID);
 static auth_param_type_desc_t scp_fw_hash = AUTH_PARAM_TYPE_DESC(
 		AUTH_PARAM_HASH, SCP_FW_HASH_OID);
 static auth_param_type_desc_t soc_fw_hash = AUTH_PARAM_TYPE_DESC(
@@ -125,6 +131,20 @@ static const auth_img_desc_t cot_desc[] = {
 					.ptr = (void *)tb_fw_hash_buf,
 					.len = (unsigned int)HASH_DER_LEN
 				}
+			},
+			[1] = {
+				.type_desc = &tb_fw_config_hash,
+				.data = {
+					.ptr = (void *)tb_fw_config_hash_buf,
+					.len = (unsigned int)HASH_DER_LEN
+				}
+			},
+			[2] = {
+				.type_desc = &hw_config_hash,
+				.data = {
+					.ptr = (void *)hw_config_hash_buf,
+					.len = (unsigned int)HASH_DER_LEN
+				}
 			}
 		}
 	},
@@ -142,6 +162,36 @@ static const auth_img_desc_t cot_desc[] = {
 			}
 		}
 	},
+	/* HW Config */
+	[HW_CONFIG_ID] = {
+		.img_id = HW_CONFIG_ID,
+		.img_type = IMG_RAW,
+		.parent = &cot_desc[TRUSTED_BOOT_FW_CERT_ID],
+		.img_auth_methods = {
+			[0] = {
+				.type = AUTH_METHOD_HASH,
+				.param.hash = {
+					.data = &raw_data,
+					.hash = &hw_config_hash,
+				}
+			}
+		}
+	},
+	/* TB FW Config */
+	[TB_FW_CONFIG_ID] = {
+		.img_id = TB_FW_CONFIG_ID,
+		.img_type = IMG_RAW,
+		.parent = &cot_desc[TRUSTED_BOOT_FW_CERT_ID],
+		.img_auth_methods = {
+			[0] = {
+				.type = AUTH_METHOD_HASH,
+				.param.hash = {
+					.data = &raw_data,
+					.hash = &tb_fw_config_hash,
+				}
+			}
+		}
+	},
 	/*
 	 * Trusted key certificate
 	 */

fdts/fvp-base-gicv2-psci-aarch32.dts

@@ -279,7 +279,7 @@
 				<0 0 41 &gic 0 41 4>,
 				<0 0 42 &gic 0 42 4>;
 
-		/include/ "rtsm_ve-motherboard.dtsi"
+		/include/ "rtsm_ve-motherboard-aarch32.dtsi"
 	};
 
 	panels {

fdts/fvp-base-gicv3-psci-aarch32.dts

@@ -288,7 +288,7 @@
 				<0 0 41 &gic 0 0 0 41 4>,
 				<0 0 42 &gic 0 0 0 42 4>;
 
-		/include/ "rtsm_ve-motherboard.dtsi"
+		/include/ "rtsm_ve-motherboard-aarch32.dtsi"
 	};
 
 	panels {

fdts/rtsm_ve-motherboard-aarch32.dtsi

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+	motherboard {
+		arm,v2m-memory-map = "rs1";
+		compatible = "arm,vexpress,v2m-p1", "simple-bus";
+		#address-cells = <2>; /* SMB chipselect number and offset */
+		#size-cells = <1>;
+		#interrupt-cells = <1>;
+		ranges;
+
+		flash@0,00000000 {
+			compatible = "arm,vexpress-flash", "cfi-flash";
+			reg = <0 0x00000000 0x04000000>,
+			      <4 0x00000000 0x04000000>;
+			bank-width = <4>;
+		};
+
+		vram@2,00000000 {
+			compatible = "arm,vexpress-vram";
+			reg = <2 0x00000000 0x00800000>;
+		};
+
+		ethernet@2,02000000 {
+			compatible = "smsc,lan91c111";
+			reg = <2 0x02000000 0x10000>;
+			interrupts = <15>;
+		};
+
+		v2m_clk24mhz: clk24mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+			clock-output-names = "v2m:clk24mhz";
+		};
+
+		v2m_refclk1mhz: refclk1mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1000000>;
+			clock-output-names = "v2m:refclk1mhz";
+		};
+
+		v2m_refclk32khz: refclk32khz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+			clock-output-names = "v2m:refclk32khz";
+		};
+
+		iofpga@3,00000000 {
+			compatible = "arm,amba-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 3 0 0x200000>;
+
+			v2m_sysreg: sysreg@010000 {
+				compatible = "arm,vexpress-sysreg";
+				reg = <0x010000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			v2m_sysctl: sysctl@020000 {
+				compatible = "arm,sp810", "arm,primecell";
+				reg = <0x020000 0x1000>;
+				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
+				clock-names = "refclk", "timclk", "apb_pclk";
+				#clock-cells = <1>;
+				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+			};
+
+			aaci@040000 {
+				compatible = "arm,pl041", "arm,primecell";
+				reg = <0x040000 0x1000>;
+				interrupts = <11>;
+				clocks = <&v2m_clk24mhz>;
+				clock-names = "apb_pclk";
+			};
+
+			mmci@050000 {
+				compatible = "arm,pl180", "arm,primecell";
+				reg = <0x050000 0x1000>;
+				interrupts = <9 10>;
+				cd-gpios = <&v2m_sysreg 0 0>;
+				wp-gpios = <&v2m_sysreg 1 0>;
+				max-frequency = <12000000>;
+				vmmc-supply = <&v2m_fixed_3v3>;
+				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+				clock-names = "mclk", "apb_pclk";
+			};
+
+			kmi@060000 {
+				compatible = "arm,pl050", "arm,primecell";
+				reg = <0x060000 0x1000>;
+				interrupts = <12>;
+				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+				clock-names = "KMIREFCLK", "apb_pclk";
+			};
+
+			kmi@070000 {
+				compatible = "arm,pl050", "arm,primecell";
+				reg = <0x070000 0x1000>;
+				interrupts = <13>;
+				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+				clock-names = "KMIREFCLK", "apb_pclk";
+			};
+
+			v2m_serial0: uart@090000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x090000 0x1000>;
+				interrupts = <5>;
+				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+				clock-names = "uartclk", "apb_pclk";
+			};
+
+			v2m_serial1: uart@0a0000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x0a0000 0x1000>;
+				interrupts = <6>;
+				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+				clock-names = "uartclk", "apb_pclk";
+			};
+
+			v2m_serial2: uart@0b0000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x0b0000 0x1000>;
+				interrupts = <7>;
+				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+				clock-names = "uartclk", "apb_pclk";
+			};
+
+			v2m_serial3: uart@0c0000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x0c0000 0x1000>;
+				interrupts = <8>;
+				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+				clock-names = "uartclk", "apb_pclk";
+			};
+
+			wdt@0f0000 {
+				compatible = "arm,sp805", "arm,primecell";
+				reg = <0x0f0000 0x1000>;
+				interrupts = <0>;
+				clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
+				clock-names = "wdogclk", "apb_pclk";
+			};
+
+			v2m_timer01: timer@110000 {
+				compatible = "arm,sp804", "arm,primecell";
+				reg = <0x110000 0x1000>;
+				interrupts = <2>;
+				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
+				clock-names = "timclken1", "timclken2", "apb_pclk";
+			};
+
+			v2m_timer23: timer@120000 {
+				compatible = "arm,sp804", "arm,primecell";
+				reg = <0x120000 0x1000>;
+				interrupts = <3>;
+				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
+				clock-names = "timclken1", "timclken2", "apb_pclk";
+			};
+
+			rtc@170000 {
+				compatible = "arm,pl031", "arm,primecell";
+				reg = <0x170000 0x1000>;
+				interrupts = <4>;
+				clocks = <&v2m_clk24mhz>;
+				clock-names = "apb_pclk";
+			};
+
+			clcd@1f0000 {
+				compatible = "arm,pl111", "arm,primecell";
+				reg = <0x1f0000 0x1000>;
+				interrupts = <14>;
+				clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
+				clock-names = "clcdclk", "apb_pclk";
+				mode = "XVGA";
+				use_dma = <0>;
+				framebuffer = <0x18000000 0x00180000>;
+			};
+
+			virtio_block@0130000 {
+				compatible = "virtio,mmio";
+				reg = <0x130000 0x1000>;
+				interrupts = <0x2a>;
+			};
+		};
+
+		v2m_fixed_3v3: fixedregulator@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		mcc {
+			compatible = "arm,vexpress,config-bus", "simple-bus";
+			arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+			v2m_oscclk1: osc@1 {
+				/* CLCD clock */
+				compatible = "arm,vexpress-osc";
+				arm,vexpress-sysreg,func = <1 1>;
+				freq-range = <23750000 63500000>;
+				#clock-cells = <0>;
+				clock-output-names = "v2m:oscclk1";
+			};
+
+			/*
+			 * Not supported in FVP models
+			 *
+			 * reset@0 {
+			 * 	compatible = "arm,vexpress-reset";
+			 * 	arm,vexpress-sysreg,func = <5 0>;
+			 * };
+			 */
+
+			muxfpga@0 {
+				compatible = "arm,vexpress-muxfpga";
+				arm,vexpress-sysreg,func = <7 0>;
+			};
+
+			/*
+			 * Not used - Superseded by PSCI sys_poweroff
+			 *
+			 * shutdown@0 {
+			 * 	compatible = "arm,vexpress-shutdown";
+			 * 	arm,vexpress-sysreg,func = <8 0>;
+			 * };
+			 */
+
+			/*
+			 * Not used - Superseded by PSCI sys_reset
+			 *
+			 * reboot@0 {
+			 * 	compatible = "arm,vexpress-reboot";
+			 * 	arm,vexpress-sysreg,func = <9 0>;
+			 * };
+			 */
+
+			dvimode@0 {
+				compatible = "arm,vexpress-dvimode";
+				arm,vexpress-sysreg,func = <11 0>;
+			};
+		};
+	};

include/bl1/bl1.h

 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -71,5 +71,9 @@ CASSERT(FWU_NUM_SMC_CALLS == 	\
 		(FWU_SMC_FID_END - FWU_SMC_FID_START + 1),\
 		assert_FWU_NUM_SMC_CALLS_mismatch);
 
+/* Utility functions */
+void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
+			meminfo_t *bl2_mem_layout);
+
 #endif /* __ASSEMBLY__ */
 #endif /* __BL1_FWU_H__ */

include/bl32/sp_min/platform_sp_min.h

@@ -10,8 +10,12 @@
 /*******************************************************************************
  * Mandatory SP_MIN functions
  ******************************************************************************/
+#if !ERROR_DEPRECATED
 void sp_min_early_platform_setup(void *from_bl2,
 		void *plat_params_from_bl2);
+#endif
+void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+		u_register_t arg2, u_register_t arg3);
 void sp_min_platform_setup(void);
 void sp_min_plat_runtime_setup(void);
 void sp_min_plat_arch_setup(void);

include/common/bl_common.h

@@ -9,6 +9,7 @@
 
 #include <ep_info.h>
 #include <param_header.h>
+#include <utils_def.h>
 
 #define UP	1
 #define DOWN	0
@@ -31,10 +32,10 @@
 #define IMAGE_STATE_EXECUTED			4
 #define IMAGE_STATE_INTERRUPTED			5
 
-#define IMAGE_ATTRIB_SKIP_LOADING	0x02
-#define IMAGE_ATTRIB_PLAT_SETUP		0x04
+#define IMAGE_ATTRIB_SKIP_LOADING	U(0x02)
+#define IMAGE_ATTRIB_PLAT_SETUP		U(0x04)
 
-#define INVALID_IMAGE_ID		(0xFFFFFFFF)
+#define INVALID_IMAGE_ID		U(0xFFFFFFFF)
 
 /*******************************************************************************
  * Constants to indicate type of exception to the common exception handler.

include/common/desc_image_load.h

@@ -33,7 +33,7 @@ int get_bl_params_node_index(unsigned int image_id);
 bl_mem_params_node_t *get_bl_mem_params_node(unsigned int image_id);
 bl_load_info_t *get_bl_load_info_from_mem_params_desc(void);
 bl_params_t *get_next_bl_params_from_mem_params_desc(void);
-
+void populate_next_bl_params_config(bl_params_t *bl2_to_next_bl_params);
 
 #endif /* LOAD_IMAGE_V2 */
 #endif /* __DESC_IMAGE_LOAD_H__ */

include/common/fdt_wrappers.h

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Helper functions to offer easier navigation of Device Tree Blob */
+
+#ifndef __FDT_WRAPPERS__
+#define __FDT_WRAPPERS__
+
+/* Number of cells, given total length in bytes. Each cell is 4 bytes long */
+#define NCELLS(len) ((len) / 4)
+
+int fdtw_read_cells(const void *dtb, int node, const char *prop,
+		unsigned int cells, void *value);
+int fdtw_write_inplace_cells(void *dtb, int node, const char *prop,
+		unsigned int cells, void *value);
+#endif /* __FDT_WRAPPERS__ */