- 16 Dec, 2019 4 commits
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Sandrine Bailleux authored
Change-Id: Ia4faf873f8946992737f76870ac92bc5cb3f4020 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
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Justin Chadwell authored
-Wpadded warns whenever the C compiler automatically includes any padding in a structure. Because TF-A has a large number of structures, this occurs fairly frequently and is incredibly verbose, and as such is unlikely to ever be fixed. The utility of this warning is also extremely limited - knowing that a structure includes padding does not point to the existence of an error, and is probably quite unlikely to indicate actually buggy behaviour. Therefore, it's probably best to keep this warning off at all times. Change-Id: I0797cb75f06b4fea0d2fdc16fd5ad978a31d76ec Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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Sandrine Bailleux authored
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- 13 Dec, 2019 5 commits
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Soby Mathew authored
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Olivier Deprez authored
* changes: S-EL2 Support: Check for AArch64 Add support for enabling S-EL2
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Sandrine Bailleux authored
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Sandrine Bailleux authored
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Justin Chadwell authored
A function declaration declares the name of the function and the type of the parameter it returns. A function prototype is a function declaration that also specifies the type of the arguments of the function. Essentially, a function prototype helps the compiler ensure whether the function call matches the return type and the right number/type of arguments of function. A function prototype itself serves as a function declaration for new style functions. The warning flag -wmissing-prototype is good enough to check for missing function prototype and is exhaustive compared to -wmissing-declaration, therefore making the later redundant. Note that, at this point, these flags are part of WARNING1 which is not used for TF-A build by default. Several platforms use upstream libraries (such as zlib etc) which are in old style c code. After the TF-A build process is restructred using CMake framework, we plan to enable WARNING1, WARNING2 and WARNING3 incrementally as the new build platform can compile each BL binary of a particular platform with set of unique compilation flags. Change-Id: I9c6bf9da74e0840e4d2624bc12376e199953c213 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 12 Dec, 2019 4 commits
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Sandrine Bailleux authored
* changes: docs: tegra: add support for Tegra194 class of SoCs Tegra194: smmu: add support for backup multiple smmu regs Tegra194: introduce tegra_mc_def.h Tegra194: 40-bit wide memory address space Tegra194: psci: rename 'percpu_data' variable
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Soby Mathew authored
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Manish Pandey authored
When a Firmware is complied as Position Independent Executable it needs to request GDT fixup by passing size of the memory region to el3_entrypoint_common macro. The Global descriptor table fixup will be done early on during cold boot process of primary core. Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be compiled as PIE, it can simply pass fixup size to the common el3 entrypoint macro to fixup GDT. The reason for this patch was to overcome the bug introduced by SHA 330ead80 which called fixup routine for each core causing re-initializing of global pointers thus overwriting any changes done by the previous core. Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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Hadi Asyrafi authored
remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I395fed66408f536e8fefd637681e742c63621818
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- 11 Dec, 2019 2 commits
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Alexei Fedorov authored
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Ambroise Vincent authored
This function scans a string backwards from the end for the first instance of a character. Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 10 Dec, 2019 8 commits
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Varun Wadekar authored
This patch adds the Tegra194 SoC information to the nvidia-tegra.rst file. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Id649a5ff1b3f70eeee34b508edb7965e7b7a2454
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Pritesh Raithatha authored
Tegra194 supports multiple SMMU blocks. This patch adds support to save register values for SMMU0 and SMMU2, before entering the System Suspend state. Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Pritesh Raithatha authored
This patch introduces memory controller register defines for Tegra194 platforms. Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Steven Kao authored
This patch updates the memory address space, physical and virtual, to be 40-bits wide for all Tegra194 platforms. Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c Signed-off-by: Steven Kao <skao@nvidia.com>
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Varun Wadekar authored
The per CPU wake times are saved in an array called 't19x_percpu_data'. But, there is one instance in the code where the name of the variable is misspelt. This patch fixes this typographical error to fix compilation errors. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735
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Manish Pandey authored
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Alexei Fedorov authored
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Sandrine Bailleux authored
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- 09 Dec, 2019 3 commits
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Ambroise Vincent authored
Previously the .init section was created even when the reclaim flag was manually set to 0. Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Zelalem Aweke <zelalem.aweke@arm.com>
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Sandrine Bailleux authored
* changes: Add memory_map tools as a target for Make tools: Add show_memory script
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Louis Mayencourt authored
Currently tb_fw_cfg_dtb size is fixed to max, which is generally a page (but depend on the platform). Instead, read the actual size of the dtb with the libfdt "fdt_totalsize" function. This avoid flushing extra memory after updating the dtb with mbedtls heap information when shared heap is used. Change-Id: Ibec727661116429f486464a0c9f15e9760d7afe2 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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- 06 Dec, 2019 7 commits
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Artsem Artsemenka authored
Check that entry point information requesting S-EL2 has AArch64 as an execution state during context setup. Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: I447263692fed6e55c1b076913e6eb73b1ea735b7
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Achin Gupta authored
This patch adds support for enabling S-EL2 if this EL is specified in the entry point information being used to initialise a secure context. It is the caller's responsibility to check if S-EL2 is available on the system before requesting this EL through the entry point information. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Change-Id: I2752964f078ab528b2e80de71c7d2f35e60569e1
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Soby Mathew authored
* changes: libc: Consolidate the size_t and NULL definitions libc: Consolidate unified definitions libc: Unify intmax_t and uintmax_t on AArch32/64
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Bence Szépkúti authored
Consolidate the definition of size_t to one header per AArch, and the definition of NULL to one header Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Iecfbad2cf360cfb705ce7aaa981700fd16219b82
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Bence Szépkúti authored
As supporting architectures aside from AArch32 and AArch64 is not a concern, keeping identical definitions in two places for a large part of the libc seems counterproductive The int128 types were left un-unified as __int128 is not supported by gcc on AArch32 Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Idf08e6fab7e4680d9da62d3c57266ea2d80472cf
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Bence Szépkúti authored
Conceptually, these are supposed to be the largest integers representable in C, but GCC and Clang define them as long long for compatibility. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: I7c0117f3be167342814d260a371889120dcf6576
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Soby Mathew authored
* changes: Reduce space lost to object alignment imx: Fix multiple definition of ipc_handle imx: Fix missing inclusion of cdefs.h
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- 04 Dec, 2019 7 commits
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Mark Dykes authored
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Mark Dykes authored
* changes: intel: Refactor common platform code [4/5] intel: Refactor common platform code [3/5] intel: Refactor common platform code [2/5] intel: Refactor common platform code [1/5]
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Mark Dykes authored
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Manish Pandey authored
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Soby Mathew authored
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Samuel Holland authored
Currently, sections within .text/.rodata/.data/.bss are emitted in the order they are seen by the linker. This leads to wasted space, when a section with a larger alignment follows one with a smaller alignment. We can avoid this wasted space by sorting the sections. To take full advantage of this, we must disable generation of common symbols, so "common" data can be sorted along with the rest of .bss. An example of the improvement, from `make DEBUG=1 PLAT=sun50i_a64 bl31`: .text => no change .rodata => 16 bytes saved .data => 11 bytes saved .bss => 576 bytes saved As a side effect, the addition of `-fno-common` in TF_CFLAGS makes it easier to spot bugs in header files. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I073630a9b0b84e7302a7a500d4bb4b547be01d51
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Samuel Holland authored
This is not conforming C and does not compile with -fno-common. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I6535954cc567d6efa06919069b91e3f50975b073
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