1. 12 Mar, 2020 4 commits
  2. 11 Mar, 2020 24 commits
  3. 10 Mar, 2020 5 commits
  4. 09 Mar, 2020 7 commits
    • Varun Wadekar's avatar
      Tegra186: store TZDRAM base/size to scratch registers · 7d74487c
      Varun Wadekar authored
      
      
      This patch saves the TZDRAM base and size values to secure scratch
      registers, for the WB0. The WB0 reads these values and uses them to
      verify integrity of the TZDRAM aperture.
      
      Change-Id: Ic70914cb958249f06cb58025a24d13734a85e16e
      Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7d74487c
    • Jeetesh Burman's avatar
      Tegra186: add SE support to generate SHA256 of TZRAM · 4eed9c84
      Jeetesh Burman authored
      
      
      The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
      memory loses power when we enter System Suspend and so its contents are
      stored to TZDRAM, before entry. This opens up an attack vector where the
      TZDRAM contents might be tampered with when we are in the System Suspend
      mode. To mitigate this attack the SE engine calculates the hash of entire
      TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
      WB0 code will validate the TZDRAM and match the hash with the one in PMC
      scratch.
      
      This patch adds driver for the SE engine, with APIs to calculate the hash
      and store SE SHA256 hash-result to PMC scratch registers.
      
      Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
      Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      4eed9c84
    • Jeetesh Burman's avatar
      Tegra186: add support for bpmp_ipc driver · 3827aa8a
      Jeetesh Burman authored
      
      
      This patch enables the bpmp-ipc driver for Tegra186 platforms,
      to ask BPMP firmware to toggle SE clock.
      
      Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae
      Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      3827aa8a
    • Mithun Maragiri's avatar
      Tegra210: disable ERRATA_A57_829520 · be85f0f7
      Mithun Maragiri authored
      
      
      ERRATA_A57_829520 disables "indirect branch prediction" for
      EL1 on cpu reset, leading to 15% drop in CPU performance
      with coremark benchmarks.
      
      Tegra210 already has a hardware fix for ARM BUG#829520,so
      this errata is not needed.
      
      This patch disables the errata to get increased performance
      numbers.
      
      Change-Id: I0b42e8badd19a8101f6a55d80eb2d953597d3c20
      Signed-off-by: default avatarMithun Maragiri <mmaragiri@nvidia.com>
      be85f0f7
    • Pravin's avatar
      Tegra194: memctrl: add support for MIU4 and MIU5 · a69a30ff
      Pravin authored
      
      
      This patch adds support for memqual miu 4,5.
      
      The MEMQUAL engine has miu0 to miu7 in which miu6 and
      miu7 is hardwired to bypass SMMU. So only miu0 to miu5
      support is provided.
      
      Change-Id: Ib350334eec521e65f395f1c3205e2cdaf464ebea
      Signed-off-by: default avatarPravin <pt@nvidia.com>
      a69a30ff
    • Stefan Kristiansson's avatar
      Tegra194: memctrl: remove support to reconfigure MSS · 4b74f6d2
      Stefan Kristiansson authored
      
      
      As bpmp-fw is running at the same time as ATF, and
      the mss client reconfiguration sequence involves performing
      a hot flush resets on bpmp, there is a chance that bpmp-fw is
      trying to perform accesses while the hot flush is active.
      
      Therefore, the mss client reconfigure has been moved to
      System Suspend resume fw and bootloader, and it can be
      removed from here.
      
      Change-Id: I34019ad12abea9681f5e180af6bc86f2c4c6fc74
      Signed-off-by: default avatarStefan Kristiansson <stefank@nvidia.com>
      4b74f6d2
    • Varun Wadekar's avatar
      Tegra: fiq_glue: remove bakery locks from interrupt handler · f6178686
      Varun Wadekar authored
      
      
      This patch removes usage of bakery_locks from the FIQ handler, as it
      creates unnecessary dependency whenever the watchdog timer interrupt
      fires. All operations inside the interrupt handler are 'reads', so
      no need for serialization.
      
      Change-Id: I3f675e610e4dabc5b1435fdd24bc28e424f5a8e4
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      f6178686