- 08 Jul, 2020 5 commits
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Etienne Carriere authored
Introduce helper functions stm32mp_register_secure_periph_iomem() and stm32mp_register_non_secure_periph_iomem() for drivers to register a resource as secure or non-secure based on its SoC interface registers base address. These functions are stubbed when shared resources driver is not embedded (!STM32MP_SHARED_RESOURCES) so that drivers embedded in other BL stages do not bother whether they shall register or not their resources. Change-Id: Icebd05a930afc5964bc4677357da5d1b23666066 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Update implementation of stm32mp_nsec_can_access_reset() based on the registering of the shared resources. Querying registering state locks further registration of peripherals. Change-Id: I5f38f2a3481780b9a71939d95984c4821c537aa4 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Update implementation of stm32mp_nsec_can_access_clock() based on the registering of the shared resources. Querying registering state locks further registration of peripherals. Change-Id: If68f6d4a52c4742ba66244c6ea2d9afa08404137 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Define helper functions stm32mp_register_secure_periph() and stm32mp_register_non_secure_periph() for platform drivers to register a shared resource assigned to respectively secure or non-secure world. Some resources are related to clock resources. When a resource is registered as secure, ensure its clock dependencies are also registered as secure. Registering a non-secure resource does not mandate its clock dependencies are also registered as non-secure. Change-Id: I74975be8976b8d3bf18dcc807541a072803af6e3 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Define from helper functions to get a human readable string identifier from a shared resource enumerated ID. Use them to make debug traces more friendly peripheral registering functions. Change-Id: I9e207b8ce1d1e9250e242ca7e15461b9a1532f40 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 23 Jun, 2020 8 commits
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Etienne Carriere authored
Embed Arch Architecture SMCCC services in stm32mp1 SP_MIN. This service is needed by Linux kernel to setup the SMCCC conduit used by its SCMI SMC transport driver. Change-Id: I454a7ef3048a77ab73fff945e8115b60445d5841 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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Etienne Carriere authored
SCMI shared memory is used to exchange message payloads between secure SCMI services and non-secure SCMI agents. It is mapped uncached (device) mainly to conform to existing support in the Linux kernel. Note that executive messages are mostly short (few 32bit words) hence not using cache will not penalize much performances. Platform stm32mp1 shall configure ETZPC to harden properly the secure and non-secure areas of the SYSRAM address space, that before CPU accesses the shared memory when mapped non-secure. This change defines STM32MP_SEC_SYSRAM_BASE/STM32MP_SEC_SYSRAM_SIZE and STM32MP_NS_SYSRAM_BASE/STM32MP_NS_SYSRAM_SIZE. Change-Id: I71ff02a359b9668ae1c5a71b5f102cf3d310f289 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
When using SP_min as monitor, only sp_min_warm_entrypoint() is a valid secure entry point. Change-Id: I440cec798e901b11a34dd482c33b2e378a8328ab Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
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Etienne Carriere authored
Disable use of Neon VFP support for platform stm32mp1 when building with SP_MIN runtime services as these can conflict with non-secure world use of NEON support. This is preferred over a systematic backup/restore of NEON context when switching between non-secure and secure worlds. When NEON support is disabled, this is done for both BL2 and BL32 as build process uses common libraries built once for both binaries. Change-Id: I4e8808dcb6ef58fc839e6f85fd6e45cfbaa34be0 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
BL32/SP_MIN configures platform security hardening from the shared resources driver. At the end of SP_MIN initialization, all shared resources shall be assigned to secure or non-secure world by drivers. A lock prevent from further change on the resource assignation. By definition, resources not registered are assign to non-secure world since not claimed by any component on the BL. No functional change as all resources are currently in state SHRES_UNREGISTERED hence assigned to non-secure world as prior this change in stm32mp1_etzpc_early_setup() and sp_min_platform_setup(). Change-Id: Ic41fab47216c3b8b7a6a75b8358cfcec411ed941 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Get number of pins in the GPIOZ bank with helper function fdt_get_gpio_bank_pin_count(). Save the value in RAM to prevent parsing the FDT several time for the same information. Change-Id: Ie68e300804461ffce09914100a7d2962116023b5 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Define enum stm32mp_shres for platform stm32mp1. The enumerated type defines all resources that can be assigned to secure or non-secure worlds at run time for the platform. Change-Id: I5de20d72735856645f1efd0993643278e8d35bcb Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
STM32MP1 SoC includes peripheral interfaces that can be assigned to the secure world, or that can be opened to the non-secure world. This change introduces the basics of a driver that manages such resources which assignation is done at run time. It currently offers API functions that state whether a service exposed to non-secure world has permission to access a targeted clock or reset controller. Change-Id: Iff20028f41586bc501085488c03546ffe31046d8 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 03 Jun, 2020 1 commit
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Etienne Carriere authored
Use ETZPC driver to configure secure aware interfaces to assign them to non-secure world. Sp_min also configures BootROM resources and SYSRAM to assign both to secure world only. Define stm32mp15 SoC identifiers for the platform specific DECPROT instances. Change-Id: I3bec9f47b04bcba3929e4df886ddb1d5ff843089 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 01 Jun, 2020 1 commit
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Etienne Carriere authored
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value. With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting. Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code. This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change. Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 11 May, 2020 2 commits
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Etienne Carriere authored
New helper functions to get GPIO banks configuration from the FDT. stm32_get_gpio_bank_pinctrl_node() allows stm32mp platforms to differentiate specific GPIO banks when these are defined with a specific path in the FDT. fdt_get_gpio_bank_pin_count() returns the number of pins in a GPIO bank as it depends on the SoC variant. Change-Id: I4481774152b3c6bf35bf986f58e357c2f9c19176 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Relation between GPIO banks and their base address and offset address if platform dependent. This change moves helper functions stm32_get_gpio_bank_base() and stm32_get_gpio_bank_offset() from plat/st/common to plat/st/stm32mp1/. Change-Id: Id3d03e585746aa5509c6fab7d88183a92d561e3f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 05 May, 2020 2 commits
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Andre Przywara authored
Now that we have an implementation for getting the node offset of the stdout-path property in the generic fdt_wrappers code, use that to replace the current ST platform specific implementation. Change-Id: I5dd05684e7ca3cb563b5f71c885e1066393e057e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
The STM32 platform port parse DT nodes to find base address to peripherals. It does this by using its own implementation, even though this functionality is generic and actually widely useful outside of the STM32 code. Re-implement fdt_get_reg_props_by_name() on top of the newly introduced fdt_get_reg_props_by_index() function, and move it to fdt_wrapper.c. This is removes the assumption that #address-cells and #size-cells are always one. Change-Id: I6d584930262c732b6e0356d98aea50b2654f789d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 29 Apr, 2020 1 commit
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Andre Przywara authored
The STM32 platform code uses its own set of FDT helper functions, although some of them are fairly generic. Remove the implementation of fdt_read_uint32_default() and implement it on top of the newly introduced fdt_read_uint32() function, then convert all users over. This also fixes two callers, which were slightly abusing the "default" semantic. Change-Id: I570533362b4846e58dd797a92347de3e0e5abb75 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 28 Apr, 2020 1 commit
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Andre Przywara authored
The device tree parsing code for the STM32 platform is using its own FDT helper functions, some of them being rather generic. In particular the existing fdt_read_uint32_array() implementation is now almost identical to the new generic code in fdt_wrappers.c, so we can remove the ST specific version and adjust the existing callers. Compared to the original ST implementation the new version takes a pointer to the DTB as the first argument, and also swaps the order of the number of cells and the pointer. Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 26 Mar, 2020 4 commits
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Yann Gautier authored
Instead of using dt_get_ddr_size() and withdrawing the secure and shared memory areas, use stm32mp_get_ddr_ns_size() function. Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
DTB and BL32 area should not be set as executable in MMU during BL2 execution, hence set those areas as MT_RO_DATA. Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
A speculative accesses to DDR could be done whereas it was not reachable and could lead to bus stall. To correct this the dynamic mapping in MMU is used. A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute, once DDR access is setup. It is then unmapped and a new mapping DDR is done with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE) load. The disabling of cache during DDR tests is also removed, as now useless. A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done instead. PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32. BL33 max size is also updated to take into account the secure and shared memory areas. Those are used in OP-TEE case. Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This function gets the DDR size from DT, and withdraws (if defined) the sizes of secure DDR and shared memory areas. This function also checks DT values fits the default DDR range. This non-secure memory is available for BL33 and non-secure OS. Change-Id: I162ae5e990a0f9b6b7d07e539de029f1d61a391b Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 23 Mar, 2020 2 commits
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Yann Gautier authored
This warning was issued by cppcheck in our downstream code: [plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]: (warning) Identical condition 'node<0', second condition is always false The second test has to check variable pwr_regulators_node. Change-Id: I4a20c4a3ac0ef0639c2df36309d90a61c02b511f Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Correct the following sparse warnings: plat/st/common/stm32mp_dt.c:103:5: warning: symbol 'fdt_get_node_parent_address_cells' was not declared. Should it be static? plat/st/common/stm32mp_dt.c:123:5: warning: symbol 'fdt_get_node_parent_size_cells' was not declared. Should it be static? As those 2 functions are only used by assert(), put them under ENABLE_ASSERTIONS flag. Change-Id: Iad721f12128df83a3de3f53e7920a9c1dce64c56 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 25 Feb, 2020 6 commits
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Ahmad Fatoum authored
Board Support for the stm32mp1 platform is contained in the device tree, so if we remove hardcoding of board name from the Makefile, we can build the intermediary objects once and generate one new tf-a-*.stm32 binary for every device tree specified. All in one go. With implicit rules implemented, we only need to change the top level target to support multi-image builds on the stm32mp1. Change-Id: I4cae7d32a4c03a3c29c559dc5332e002223902c1 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Ahmad Fatoum authored
Board Support for the stm32mp1 platform is contained in the device tree, so if we remove hardcoding of board name from the Makefile, we can build the intermediary objects once and generate one new tf-a-*.stm32 binary for every device tree specified. All in one go. Prepare for this by employing implicit rules. Change-Id: I5a022a89eb12696cd8cee7bf28ac6be54849901f Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Ahmad Fatoum authored
Doing this allows us in the next commit to use implicit rules (%-patterns) to cover all the images we generate during a stm32mp1 build. Change-Id: Ibde59d10ccce42566f82820117d7fd0d77345e6c Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Ahmad Fatoum authored
The linker script has no board-specific information that necessitates it having a name derived from the board name. Give it a fixed name, so we can later reuse the same linker script for multiple boards. Change-Id: Ie6650f00389f4ab8577ae82a36c620af9c64101e Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Ahmad Fatoum authored
Currently, building TF-A for STM32MP1 triggers a full rebuild, avoid this by removing the .PHONY: specification for the final image and replace it by specifying PHONYness for the targets that don't actually produce file output. This will come in handy in follow-up commits, when implicit rules are introduced, as implicit rule search is skipped for .PHONY targets. Change-Id: Ib9966479032b081a54123b99f889760e85639f19 Fixes: f74cbc93 ("stm32mp1: Link BL2, BL32 and DTB in one binary") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 28 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I3421336230981d4cda301fa2cef24b94b08353b1
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- 20 Jan, 2020 5 commits
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Lionel Debieve authored
STM32MP1 platform is able to boot from SPI-NOR devices. These modifications add this support using the new SPI-NOR framework. Change-Id: I75ff9eba4661f9fb87ce24ced2bacbf8558ebe44 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
STM32MP1 platform is able to boot from SPI-NAND devices. These modifications add this support using the new SPI-NAND framework. Change-Id: I0d5448bdc4bde153c1209e8043846c0f935ae5ba Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
STM32MP1 platform is able to boot from raw NAND devices. These modifications add this support using the new raw NAND framework. Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Nicolas Le Bayon authored
For STM32MP1, the address space is 4GB, which can be first divided in 4 parts of 1GB. This LVL1 table is already mapped regardless of MAX_XLAT_TABLES. Fixing typo: Replace Ko to KB. BL2/sp_min for platform STM32MP1 requires 4 MMU translation tables: - a level2 table and a level3 table for identity mapped SYSRAM - a level2 table mapping 2MB of BootROM runtime resources - a level2 table mapping 2MB of secure DDR (case BL32 is OP-TEE) Change-Id: If80cbd4fccc7689b39dd540d6649b1313557f326 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Add a new entry to find register properties by name and include new assert functions to limit address cells to 1 and size cells to 1. Change-Id: Ide59a795a05fb2af36bd07fec15e5a3adf196226 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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