- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 29 Nov, 2018 1 commit
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Ryan Grachek authored
This is needed to utilize the DMA controller on the hikey960 Signed-off-by: Ryan Grachek <ryan@edited.us>
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- 08 Nov, 2018 1 commit
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Jerome Forissier authored
Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1. Enables building with ERROR_DEPRECATED=1. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Migrate to new GIC interfaces. - Remove unused bl1_init_bl2_mem_layout(). - Migrate to bl31_early_platform_setup2(). - Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE. - Remove references to removed build options. - Update Makefile paths. Change-Id: I583fd893555e6535f32d87ed67bbae430b8e6afe Tested-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 05 Mar, 2018 1 commit
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Haojian Zhuang authored
Since LOAD_IMAGE_V2 is always enabled in HiKey960 platform. Drop LOAD_IMAGE v1 to simplify code. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 22 Jan, 2018 1 commit
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Leo Yan authored
When some interrupts are configured as group 0 in GICv2, these interrupts trigger FIQ signal; this results in the Linux kernel panic by reporting log: "Bad mode in FIQ handler detected on CPU0, code 0x00000000 -- Unknown/Uncategorized". Unfortunately from kernel side it has no permission to read the GIC register for group 0 interrupts so we have no chance to get to know which interrupt is configured as secure interrupt and cause the kernel panic. For upper reason, this commit enables FIQ exception handling for SPD_none case. If the system has not enabled SPD the FIQ interrupt is trapped into EL3 and the FIQ handler can report the interrupt number so we can easily narrow down which FIQ introduce unexpected interrupt. After enable SPD we can rely on SPD interrupt route model to handle FIQ. Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 01 Sep, 2017 2 commits
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 07 Jun, 2017 1 commit
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Haojian Zhuang authored
Support BL31 on HiKey960 platform. Implement PSCI. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 31 May, 2017 1 commit
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Leo Yan authored
The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port for cluster 0 in BL31 platform setup flow. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 24 May, 2017 1 commit
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Haojian Zhuang authored
Support BL31 and PSCI. Enable multiple cores in PSCI. Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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