- 26 Mar, 2021 1 commit
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Andre Przywara authored
When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure we tell the non-secure world about the memory region it uses. Add a reserved-memory node to the DT, which covers the area that BL31 could occupy. The "no-map" property will prevent OSes from mapping the area, so there would be no speculative accesses. Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1 Signed-off-by:Andre Przywara <andre.przywara@arm.com>
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- 25 Mar, 2021 10 commits
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Andre Przywara authored
The new Allwinner H616 SoC lacks the management controller and the secure SRAM A2, so we need to tweak the memory map quite substantially: We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our compressed virtual address space (max 256MB) anymore, so we revert to the full 32bit VA space and use a flat mapping throughout all of it. The missing controller also means we need to always use the native PSCI ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC. Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d Signed-off-by: -
Andre Przywara authored
Change-Id: I557fd05401e24204952135cf3ca26479a43ad1f1 Signed-off-by: -
Andre Przywara authored
In preparation for changing the memory map, express the locations of the various code and data pieces more dynamically, allowing SoCs to override the memmap later. Also prepare for the SCP region to become optional. No functional change. Change-Id: I7ac01e309be2f23bde2ac2050d8d5b5e3d6efea2 Signed-off-by: -
Andre Przywara authored
The code to power the current core off when SCPI is not available is now different for the two supported SoC families. To make adding new platforms easier, move sunxi_cpu_power_off_self() into the SoC directory, so we don't need to carry definitions for both methods for all SoCs. On the H6 we just need to trigger the CPUIDLE hardware, so can get rid of all the code to program the ARISC, which is now only needed for the A64 version. Change-Id: Id2a1ac7dcb375e2fd021b441575ce86b4d7edf2c Signed-off-by: -
Andre Przywara authored
For the existing SoCs we support, we use SEPARATE_NOBITS_REGION, to move some parts of the data into separate memory regions (to save on the SRAM A2 we are loaded into). For the upcoming H616 platform this is of no concern (we run in DRAM), so make this flag a platform choice instead. Change-Id: Ic01d49578c6274660f8f112bd23680d3eca3be7a Signed-off-by: -
Andre Przywara authored
Update the Allwinner platform documentation. Reorder the section, to have the build instructions first, followed by hints about the installation. Add some ASCII art about the layout of our virtual memory map, which uses a non-trivial condensed virtual address space. Change-Id: Iaaa79b4366012394e15e4c1b26c212b5efb6ed6a Signed-off-by: -
André Przywara authored
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André Przywara authored
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Andre Przywara authored
The upcoming refactoring to support the new H616 SoCs will push the A64 build over the edge, by using more than the 48KB of SRAM available. To reduce the code size, set some libfdt options that aim to reduce sanity checks (for saving code space): - ASSUME_LATEST: only allow v17 DTBs (as created by dtc) - ASSUME_NO_ROLLBACK: don't prepare for failed DT additions - ASSUME_LIBFDT_ORDER: assume sane ordering, as done by dtc Change-Id: I12c93ec09e7587c5ae71e54947f817c32ce5fd6d Signed-off-by: -
André Przywara authored
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- 24 Mar, 2021 29 commits
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Joanna Farley authored
* changes: nxp lx2160a-aqds: new plat based on soc lx2160a NXP lx2160a-rdb: new plat based on SoC lx2160a nxp lx2162aqds: new plat based on soc lx2160a nxp: errata handling at soc level for lx2160a nxp: make file for loading additional ddr image nxp: adding support of soc lx2160a nxp: deflt hdr files for soc & their platforms nxp: platform files for bl2 and bl31 setup nxp: warm reset support to retain ddr content nxp: nv storage api on platforms nxp: supports two mode of trusted board boot nxp: fip-handler for additional fip_fuse.bin nxp: fip-handler for additional ddr-fip.bin nxp: image loader for loading fip image nxp: svp & sip smc handling nxp: psci platform functions used by lib/psci nxp: helper function used by plat & common code nxp: add data handler used by bl31 nxp: adding the driver.mk file nxp-tool: for creating pbl file from bl2 nxp: adding the smmu driver nxp: cot using nxp internal and mbedtls nxp:driver for crypto h/w accelerator caam nxp:add driver support for sd and emmc nxp:add qspi driver nxp: add flexspi driver support nxp: adding gic apis for nxp soc nxp: gpio driver support nxp: added csu driver nxp: driver pmu for nxp soc nxp: ddr driver enablement for nxp layerscape soc nxp: i2c driver support. NXP: Driver for NXP Security Monitor NXP: SFP driver support for NXP SoC NXP: Interconnect API based on ARM CCN-CCI driver NXP: TZC API to configure ddr region NXP: Timer API added to enable ARM generic timer nxp: add dcfg driver nxp:add console driver for nxp platform tools: add mechanism to allow platform specific image UUID tbbr-cot: conditional definition for the macro tbbr-cot: fix the issue of compiling time define cert_create: updated tool for platform defined certs, keys & extensions tbbr-tools: enable override TRUSTED_KEY_CERT
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André Przywara authored
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Pankaj Gupta authored
New NXP platform lx2160a-qds: - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by:
Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by:
Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I500ddbe9e56c4af5f955da6ecbd4ddc5fbe89a12
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Pankaj Gupta authored
New NXP platform lx2160a-rdb(Reference Design Board): - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by:
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Pankaj Gupta authored
New NXP platform lx2162aqds: - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by:
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Pankaj Gupta authored
SoC erratas are handled as part of this commit. Signed-off-by: -
Pankaj Gupta authored
- NXP SoC lx2160a needs additional ddr_fip.bin. - There are three types of ddr image that can be created: -- ddr_fip.mk for creating fip_ddr.bin image for normal boot. -- ddr_fip_sb.mk for creating fip_ddr_sec.bin image for NXP CSF based CoT/secure boot. -- ddr_fip_tbbr.mk for creating fip_ddr_sec.bin image for MBEDTLS CoT/secure boot. Signed-off-by: -
Pankaj Gupta authored
* NXP SoC is 16 A-72 core SoC. * SoC specific defines are defined in: - soc.def - soc.h * Called for BL2 and BL31 setup, SoC specific setup are implemented in: - soc.c * platform specific helper functions implemented at: - aarch64/lx2160a_helpers.S * platform specific functions used by 'plat/nxp/commpon/psci', etc. are implemented at: - aarch64/lx2160a.S * platform specific implementation for handling PSCI_SYSTEM_RESET2: - aarch64/lx2160a_warm_rst.S Signed-off-by:
rocket <rod.dorris@nxp.com> Signed-off-by:
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Pankaj Gupta authored
- Default header files for: -- plat/nxp/soc-lxxxx/include/soc.h uses: --- soc_default_base_addr.h --- soc_default_base_macros.h -- plat/nxp/soc-lxxxx/<$PLAT>/platform_def.h uses: --- plat_default_def.h: Every macro define can be overidden. -- include/common/tbbr/tbbr_img_def.h uses: --- plat_tbbr_img_def.h: platform specific new FIP image macros. Signed-off-by: -
Pankaj Gupta authored
For NXP platforms: - Setup files for BL2 and BL31 - Other supporting files. Signed-off-by: -
Pankaj Gupta authored
NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2 raised from kernel (> 5.4). As part of first cold boot, DDR training data is stored in NV storage. As part of this SMC handling, following things are done: - DDR is put in self-refresh mode to retain the content of DDR. - Reset cause is saved. - Reset is triggered. On next boot to last warm-reset, DDR training is restored from the NV storage. Signed-off-by:
Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by:
Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by:
Priyanka Singh <priyanka.singh@nxp.com> Signed-off-by:
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Pankaj Gupta authored
NV storage API(s) for NXP platforms, supported on: - flexspi-nor - SecMon - General Purpose Registers at Low-Power section, retains their content if backed by coined battery. Signed-off-by: -
Pankaj Gupta authored
NXP SoC supports two TBB mode: - MBED_TLS based -- ROTK key hash is placed as part of the BL2 binary at section: --- .rodata.nxp_rotpk_hash -- Supporting non-volatile counter via SFP. -- platform function used by TFA common authentication code. - NXP CSF based -- ROTK key deployment vary from MBEDTLS Signed-off-by:Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by:
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Pankaj Gupta authored
All of the NXP SoC, needs fip_fuse image to be loaded additionally as part of preparation for Trusted board boot - fip_fuse.bin contains an image for auto fuse provisioning. - Auto fuse provisioning is based on the input file with values for: -- SRK Hash -- OTPMK -- misc. refer board manual for more details. Signed-off-by: -
Pankaj Gupta authored
Few of the NXP SoC like LX2160A, needs ddr-phy images to be loaded additionally before DDR initialization - fip_ddr.bin is created containing upto 6 ddr images. - With TRUSTED_BOARD_BOOT = 1, fip_ddr.bin is authenticated first before loading and starting DDR initialization. - To successfully compile this image, platform-defined header files needs to be defined: -- include/common/tbbr/tbbr_img_def.h uses: --- plat_tbbr_img_def.h: platform specific new FIP image macros. -- include/tools/share/firmware_image_package.h uses: --- plat_def_fip_uuid.h: platform specific new UUID macros. ---- Added UUID for DDR images to create FIP-DDR. ---- Added UUID for FUSE provisioning images to create FIP-fuse. -- include/tools/share/tbbr_oid.h uses: --- platform_oid.h: platform specific new OID macros. Signed-off-by: -
Pankaj Gupta authored
function load_img(), is dependent on: - Recursively calling load_image() defined in common/bl_common.c - for each image in the fip. Signed-off-by: -
Pankaj Gupta authored
SMC call handling at EL3 due SIP and SVC calls. Signed-off-by:
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Pankaj Gupta authored
Signed-off-by:
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Pankaj Gupta authored
Signed-off-by:
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Pankaj Gupta authored
bl31-data file written in assembly helps to manage data at bl31. Signed-off-by:
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Pankaj Gupta authored
Signed-off-by: -
Pankaj Gupta authored
NXP tool to create pbl from bl2 binary: - RCW is prepended to BL2.bin - If TRUSTED_BOARD_BOOT=1, pre-append the CSF header to be understood by NXP boot-rom. Signed-off-by: -
Pankaj Gupta authored
NXP SMMU driver API for NXP SoC. - Currently it supports by-passing SMMU, called only when NXP CAAM is enabled. - (TBD) AMQ based SMMU access control: Access Management Qualifiers (AMQ) advertised by a bus master for a given transaction. Signed-off-by: -
Pankaj Gupta authored
Chain of trust(CoT) is enabled on NXP SoC in two ways: - Using MbedTLS, parsing X509 Certificates. - Using NXP internal method parsing CSF header Signed-off-by:
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Pankaj Gupta authored
NXP has hardware crypto accelerator called CAAM. - Work with Job ring - Jobs are submitted to CAAM in the form of 64 word descriptor. Signed-off-by:
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Pankaj Gupta authored
SD & eMMC driver support for NXP SoC. Signed-off-by:
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Pankaj Gupta authored
NXP QuadSPI driver support NXP SoC. - Supporting QSPI flash Signed-off-by: -
Kuldeep Singh authored
Flexspi driver now introduces read/write/erase APIs for complete flash size, FAST-READ are by default used and IP bus is used for erase, read and write using flexspi APIs. Framework layer is currently embedded in driver itself using flash_info defines. Test cases are also added to confirm flash functionality currently under DEBUG flag. Signed-off-by:
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Pankaj Gupta authored
GIC api used by NXP SoC is based on: - arm provided drivers: /drivers/arm/gic Signed-off-by:
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