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  1. 26 Mar, 2021 1 commit
    • Andre Przywara's avatar
      allwinner: H616: Add reserved-memory node to DT · 0be10ee3
      Andre Przywara authored 
      

When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.

Add a reserved-memory node to the DT, which covers the area that BL31
could occupy. The "no-map" property will prevent OSes from mapping
the area, so there would be no speculative accesses.

Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      0be10ee3
  3. 25 Mar, 2021 6 commits
    • Andre Przywara's avatar
      allwinner: Add Allwinner H616 SoC support · 26123ca3
      Andre Przywara authored 
      

The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.

The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.

Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      26123ca3
    • Andre Przywara's avatar
      allwinner: Add H616 SoC ID · bb104f27
      Andre Przywara authored 
      

Change-Id: I557fd05401e24204952135cf3ca26479a43ad1f1
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      bb104f27
    • Andre Przywara's avatar
      allwinner: Express memmap more dynamically · 01cec8f4
      Andre Przywara authored 
      

In preparation for changing the memory map, express the locations of the
various code and data pieces more dynamically, allowing SoCs to override
the memmap later.
Also prepare for the SCP region to become optional.

No functional change.

Change-Id: I7ac01e309be2f23bde2ac2050d8d5b5e3d6efea2
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      01cec8f4
    • Andre Przywara's avatar
      allwinner: Move sunxi_cpu_power_off_self() into platforms · 9227719d
      Andre Przywara authored 
      

The code to power the current core off when SCPI is not available is now
different for the two supported SoC families.
To make adding new platforms easier, move sunxi_cpu_power_off_self()
into the SoC directory, so we don't need to carry definitions for both
methods for all SoCs.

On the H6 we just need to trigger the CPUIDLE hardware, so can get rid
of all the code to program the ARISC, which is now only needed for the
A64 version.

Change-Id: Id2a1ac7dcb375e2fd021b441575ce86b4d7edf2c
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      9227719d
    • Andre Przywara's avatar
      allwinner: Move SEPARATE_NOBITS_REGION to platforms · eb15bdaa
      Andre Przywara authored 
      

For the existing SoCs we support, we use SEPARATE_NOBITS_REGION, to move
some parts of the data into separate memory regions (to save on the SRAM
A2 we are loaded into).
For the upcoming H616 platform this is of no concern (we run in DRAM),
so make this flag a platform choice instead.

Change-Id: Ic01d49578c6274660f8f112bd23680d3eca3be7a
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      eb15bdaa
    • Andre Przywara's avatar
      allwinner: A64: Limit FDT checks to reduce code size · 8fa5592b
      Andre Przywara authored 
      

The upcoming refactoring to support the new H616 SoCs will push the A64
build over the edge, by using more than the 48KB of SRAM available.

To reduce the code size, set some libfdt options that aim to reduce
sanity checks (for saving code space):
- ASSUME_LATEST: only allow v17 DTBs (as created by dtc)
- ASSUME_NO_ROLLBACK: don't prepare for failed DT additions
- ASSUME_LIBFDT_ORDER: assume sane ordering, as done by dtc

Change-Id: I12c93ec09e7587c5ae71e54947f817c32ce5fd6d
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      8fa5592b
  5. 24 Mar, 2021 18 commits
  7. 23 Mar, 2021 1 commit
  9. 22 Mar, 2021 1 commit
  11. 19 Mar, 2021 1 commit
  13. 16 Mar, 2021 1 commit
  15. 15 Mar, 2021 1 commit
    • Olivier Deprez's avatar
      SPM: declare third cactus instance as UP SP · e96fc8e7
      Olivier Deprez authored 
      

The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.
Signed-off-by: default avatarOlivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
      e96fc8e7
  17. 10 Mar, 2021 1 commit
  19. 09 Mar, 2021 1 commit
  21. 08 Mar, 2021 1 commit
  23. 03 Mar, 2021 6 commits
  25. 02 Mar, 2021 1 commit