- 05 May, 2021 1 commit
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Zelalem authored
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I97b2c5c5cfbf4ddb055d0f7a5ab04386460db060
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- 30 Apr, 2021 3 commits
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Zelalem authored
This is the first release of the public Trusted Firmware A class threat model. This release provides the baseline for future updates to be applied as required by developments to the TF-A code base. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I3c9aadc46196837679f0b1377bec9ed4fc42ff11
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laurenw-arm authored
Updated the list of supported FVP platforms as per the latest FVP release. Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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Olivier Deprez authored
PSA wording is not longer associated with FF-A. Change-Id: Id7c53b9c6c8f383543f6a32a15eb15b7749d8658 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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- 29 Apr, 2021 1 commit
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Manish V Badarkhe authored
Documented the build options used in Arm GPT parser enablement. Change-Id: I9d7ef2f44b8f9d2731dd17c2639e5ed0eb6d0b3a Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 28 Apr, 2021 2 commits
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Madhukar Pappireddy authored
Updated tentative code freeze and release target date for v2.6 release. Change-Id: I3dd6cfef1a07f3e0159ec7996d18f6cbcb975da7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Madhukar Pappireddy authored
Updated code freeze and release target date for v2.5 release. Change-Id: I72850eed2aa77d3adecaf71d74e9ecebcc36d5b4 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 27 Apr, 2021 2 commits
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Pali Rohár authored
This new compile option is only for Armada 3720 Development Board. When it is set to 1 then TF-A will setup PM wake up src configuration. By default this new option is disabled as it is board specific and no other A37xx board has PM wake up src configuration. Currently neither upstream U-Boot nor upstream Linux kernel has wakeup support for A37xx platforms, so having it disabled does not cause any issue. Prior this commit PM wake up src configuration specific for Armada 3720 Development Board was enabled for every A37xx board. After this change it is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1 Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
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Aditya Angadi authored
A Neoverse reference design platform can have two or more variants that differ in core count, cluster count or other peripherals. To allow reuse of platform code across all the variants of a platform, introduce build option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design platforms. The range of allowed values for the build option is platform specific. The recommended range is an interval of non negative integers. An example usage of the build option is make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1 Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 26 Apr, 2021 1 commit
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Chris Kay authored
The `arm-gic.h` file distributed by the Linux kernel is disjunctively dual-licensed under the GPL-2.0 or MIT licenses, but the BSD-3-Clause license has been applied in violation of the requirements of both licenses. This change ensures the file is correctly licensed under the terms of the MIT license, and that we comply with it by distributing a copy of the license text. Change-Id: Ie90066753a5eb8c0e2fc95ba43e3f5bcbe2fa459 Signed-off-by: Chris Kay <chris.kay@arm.com>
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- 23 Apr, 2021 3 commits
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Manish Pandey authored
sgm775 is an old platform and is no longer maintained by Arm and its fast model FVP_CSS_SGM-775 is no longer available for download. This platform is now superseded by Total Compute(tc) platforms. This platform is now deprecated but the source will be kept for cooling off period of 2 release cycle before removing it completely. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I8fe1fc3da0c508dba62ed4fc60cbc1642e0f7f2a
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Manish Pandey authored
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ifb8a3220f2fc2286fa91614887d17f54178ed002
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Yidi Lin authored
- Add basic platform setup - Add MT8195 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: I7978e2f32e58900e5cf93f741ee8eaf8b8e3b842 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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- 21 Apr, 2021 1 commit
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Yann Gautier authored
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done for PIE support on AARCH64. The RELA_SECTION is redefined for AARCH32, as the created section is .rel.dyn and the symbols are .rel*. Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 20 Apr, 2021 4 commits
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Manish Pandey authored
As per FF-A v1.0 spec, Table 3.1, messaging method field also contains information about whether partition supports managed exit or not. Since a partition can support managed exit only if it supports direct messaging, so there are two new possible values, managed exit with only direct messaging or with both messaging methods. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ic77cfb37d70975c3a36c56f8b7348d385735f378
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Mikael Olsson authored
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode the non-secure world cannot access the registers needed to use the NPU. To still allow the non-secure world to use the NPU, a SiP service has been added that can delegate non-secure access to the registers needed to use it. Only the HW_CONFIG for the Arm Juno platform has been updated to include the device tree for the NPU and the platform currently only loads the HW_CONFIG in AArch64 builds. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
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Mikael Olsson authored
To make it possible to use the hw_config device tree for dynamic configuration in BL31 on the Arm Juno platform. A placeholder hw_config has been added that is included in the FIP and a Juno specific BL31 setup has been added to populate fconf with the hw_config. Juno's BL2 setup has been updated to align it with the new behavior implemented in the Arm FVP platform, where fw_config is passed in arg1 to BL31 instead of soc_fw_config. The BL31 setup is expected to use the fw_config passed in arg1 to find the hw_config. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6
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Konstantin Porotchkin authored
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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- 19 Apr, 2021 3 commits
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Madhukar Pappireddy authored
Change-Id: I0b38c114fd2958d2b4040585611cafa132ccfd9c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Chris Kay authored
This change adds a configuration for commitlint - a tool designed to enforce a particular commit message style - and run it as part of Git's commit-msg hook. This validates commits immediately after the editor has been exited, and the configuration is derived from the configuration we provide to Commitizen. While the configuration provided suggests a maximum header and body length, neither of these are hard errors. This is to accommodate the occasional commit where it may be difficult or impossible to comply with the length requirements (for example, with a particularly long scope, or a long URL in the message body). Change-Id: Ib5e90472fd1f1da9c2bff47703c9682232ee5679 Signed-off-by: Chris Kay <chris.kay@arm.com>
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Chris Kay authored
Husky is a tool for managing Git hooks within the repository itself. Traditionally, commit hooks need to be manually installed on a per-user basis, but Husky allows us to install these hooks either automatically when `npm install` is invoked within the repository, or manually with `npx husky install`. This will become useful for us in the next few patches when we begin introducing tools for enforcing a commit message style. Change-Id: I64cae147e9ea910347416cfe0bcc4652ec9b4830 Signed-off-by: Chris Kay <chris.kay@arm.com>
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- 14 Apr, 2021 1 commit
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Manish V Badarkhe authored
Updated the documentation with latest Mbed TLS supported version i.e. Mbed TLS v2.26.0 Fixes available in this version of Mbed TLS mainly affect key generation/writing and certificates writing, which are features used in the cert_create tool. Release notes of Mbed TLSv2.26.0 are available here: https://github.com/ARMmbed/mbedtls/releases/tag/v2.26.0 Change-Id: Ie15ee45d878b7681e15ec4bf64d54b416a31aa2f Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 09 Apr, 2021 1 commit
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Pali Rohár authored
CZ.NIC as part of Turris project released free and open source WTMI application firmware 'wtmi_app.bin' for all Armada 3720 devices. This firmware includes additional features like access to Hardware Random Number Generator of Armada 3720 SoC which original Marvell's 'fuse.bin' image does not have. CZ.NIC's Armada 3720 Secure Firmware is available at website: https://gitlab.nic.cz/turris/mox-boot-builder/ This change updates documentation to include steps how to build Marvell firmware image for Espressobin with this firmware to enable Hardware Random Number Generator on Espressobin. In this change is fixed also URL to TF-A and U-Boot git repositories in Espressobin build example. And as Marvell github repositories switched default branch to master, explicit branch via -b parameter is redundant and therefore from examples removed. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I59ee29cb6ed149264c5e4202f2af8f9ab3859418
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- 06 Apr, 2021 1 commit
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laurenw-arm authored
Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions <= r1p1. This erratum is avoided by inserting a DMB ST before acquire atomic instructions without release semantics through a series of writes to implementation defined system registers. SDEN can be found here: https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token= Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f
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- 01 Apr, 2021 3 commits
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Venkatesh Yadav Abbarapu authored
As per the new multi-console framework, updating the JTAG DCC support. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I77994ce387caf0d695986df3d01d414a920978d0
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Venkatesh Yadav Abbarapu authored
As per the new multi-console framework, updating the JTAG DCC support. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8
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Venkatesh Yadav Abbarapu authored
The legacy console is gone. Re-add DCC console support based on the multi-console framework. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: Ia8388721093bc1be3af40974530d7c9a9ae5f43e
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- 25 Mar, 2021 2 commits
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Andre Przywara authored
The new Allwinner H616 SoC lacks the management controller and the secure SRAM A2, so we need to tweak the memory map quite substantially: We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our compressed virtual address space (max 256MB) anymore, so we revert to the full 32bit VA space and use a flat mapping throughout all of it. The missing controller also means we need to always use the native PSCI ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC. Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Update the Allwinner platform documentation. Reorder the section, to have the build instructions first, followed by hints about the installation. Add some ASCII art about the layout of our virtual memory map, which uses a non-trivial condensed virtual address space. Change-Id: Iaaa79b4366012394e15e4c1b26c212b5efb6ed6a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 23 Mar, 2021 1 commit
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Ying-Chun Liu (PaulLiu) authored
Adds bl2 with FIP to the build required for mbed Linux booting where we do: BootROM -> SPL -> BL2 -> OPTEE -> u-boot If NEED_BL2 is specified then BL2 will be built and BL31 will have its address range modified upwards to accommodate. BL31 must be loaded from a FIP in this case. If NEED_BL2 is not specified then the current BL31 boot flow is unaffected and u-boot SPL will load and execute BL31 directly. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I655343b3b689b1fc57cfbedda4d3dc2fbd549a96
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- 11 Mar, 2021 2 commits
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Manish Pandey authored
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I24a1697d0e0ec9289d272f0e96a252894faf12ef
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Manish Pandey authored
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I9fafeb966eeec35527647282b953d88f6aa383be
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- 01 Mar, 2021 1 commit
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Manish V Badarkhe authored
Added GIC600AE FVP model version information. Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 25 Feb, 2021 1 commit
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johpow01 authored
ARMv8.6 adds virtual offset registers to support virtualization of the event counters in EL1 and EL0. This patch enables support for this feature in EL3 firmware. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
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- 16 Feb, 2021 1 commit
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Yann Gautier authored
Add blank lines before lists and code example. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I901646e0be74227af983079d0cbe05c6a217fab6
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- 09 Feb, 2021 1 commit
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Manish V Badarkhe authored
Added a build option 'FVP_GICR_REGION_PROTECTION' to make redistributor frame of fused/unused cores as read only. Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 05 Feb, 2021 1 commit
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Jimmy Brisson authored
This adds the TRNG Firmware Interface Service to the standard service dispatcher. This includes a method for dispatching entropy requests to platforms and includes an entropy pool implementation to avoid dropping any entropy requested from the platform. Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 02 Feb, 2021 3 commits
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Pali Rohár authored
docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image ESPRESSObin-Ultra TF-A build example was now just a copy+paste of previous mentioned example. It produced debug binary with custom log level, which was not described. So rather replace this duplicate build example by a full example with all steps how to build production release of Marvell firmware image for EspressoBin with 1GHz CPU and 1GB DDR4 RAM. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ief1b8bc96a3035ebd8421bd68dca5eb5c8d8fd52
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Pali Rohár authored
Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I192acab2a7f42cd80069faeac2d7823a05558dc6
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Pali Rohár authored
Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5310c30051703bbf9f377762a00eb6a8188c6fa1
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