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The more recent Allwinner SoCs contain an OpenRISC management
controller (called arisc or CPUS), which shares the bus with the ARM cores,
but runs on a separate power domain. This is meant to handle power
management with the ARM cores off.
There are efforts to run sophisticated firmware on that core
(communicating via SCPI with the ARM world), but for now can use it for
the rather simple task of helping to turn the ARM cores off. As this
cannot be done by ARM code itself (because execution stops at the
first of the three required steps), we can offload some instructions to
this management processor.
This introduces a helper function to hand over a bunch of instructions
and triggers execution. We introduce a bakery lock to avoid two cores
trying to use that (single) arisc core. The arisc code is expected to
put itself into reset after is has finished execution.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

There are reports that activating the DC1SW before certain other
regulators leads to the PMIC overheating and consequently shutting down.
To avoid this situation, delay the activation of the DC1SW line until
the very end, so those other lines are always activated earlier.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.

To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Now that we have a pointer to the device tree blob, let's use that to
do some initial setup of the PMIC:
- We scan the DT for the compatible string to find the PMIC node.
- We switch the N_VBUSEN pin if the DT property tells us so.
- We scan over all regulator subnodes, and switch DC1SW if there is at
least one other node referencing it (judging by the existence of a
phandle property in that subnode).
This is just the first part of the setup, a follow up patch will setup
voltages.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

For Allwinner boards we now use some heuritistics to find a preloaded
.dtb file.

Pass this address on to the PMIC setup routine, so that it can use the
information contained therein to setup some initial power rails.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The initial PMIC setup for the Allwinner platform is quite board
specific, and used to be guarded by reading the .dtb stub *name* from the
SPL image in the legacy ATF port. This doesn't scale particularly well,
and requires constant maintainance.
Instead having the actual .dtb available would be much better, as the PMIC
setup requirements could be read from there directly.
The only available BL33 for Allwinner platforms so far is U-Boot, and
fortunately U-Boot comes with the full featured .dtb, appended to the
end of the U-Boot image.

Introduce some code that scans the beginning of the BL33 image to look
for the load address, which is followed by the image size. Adding those
two values together gives us the end of the image and thus the .dtb
address. Verify that this heuristic is valid by sanitising some values
and checking the DTB magic.

Print out the DTB address and the model name, if specified in the root
node.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Boards with the Allwinner A64 SoC are mostly paired with an AXP803 PMIC,
which allows to programmatically power down the board.

Use the newly introduced RSB driver to detect and program the PMIC on
boot, then later to turn off the main voltage rails when receiving a
PSCI SYSTEM_POWER_OFF command.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

In the H6 platform code there is a routine to do the platform
initialisation of the R_I2C controller. We will need a very similar
setup routine to initialise the RSB controller on the A64.

Move this code to sunxi_common.c and generalise it to support all SoCs
and also to cover the related RSB bus.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Allwinner produces reference board designs, which apparently most board
vendors copy from. So every H5 board I checked uses regulators which are
controlled by the same PortL GPIO pins to power the ARM CPU cores, the
DRAM and the I/O ports.
Add a SoC specific power down routine, which turns those regulators off
when ATF detects running on an H5 SoC and the rich OS triggers a
SYSTEM_POWEROFF PSCI call.

NOTE: It sounds very tempting to turn the CPU power off, but this is not
working as expected, instead the system is rebooting. Most probably this
is due to VCC-SYS also being controlled by the same GPIO line, and
turning this off requires an elaborate and not fully understood setup.
Apparently not even Allwinner reference code is turning this regulator
off. So for now we refrain to pulling down PL8, the power consumption is
quite low anyway, so we are as close to poweroff as reasonably possible.
Many thanks to Samuel for doing some research on that topic.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Many boards without a dedicated PMIC contain simple regulators, which
can be controlled via GPIO pins.

To later allow turning them off easily, introduce a simple function to
configure a given pin as a GPIO out pin and set it to the desired level.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will need some of those in the platform specific code
parts as well, and want to introduce new functions shared across the
whole platform port.

So move the sunxi_private.h file into the common/include directory, so
that it becomes visible to all parts of the platform code.
Fix up the existing #includes and add missing ones, also add the
sunxi_read_soc_id() prototype here.

This will be used in follow up patches.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Some boards don't have a PMIC, so they can't easily turn their power
off. To cover those boards anyway, let's turn off as many devices and
clocks as possible, so that the power consumption is reduced. Then
halt the last core, as before.
This will later be extended with proper PMIC support for supported
boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

In the BL31 platform setup we read the Allwinner SoC ID to identify the
chip and print its name.
In addition to that we will need to differentiate the power setup
between the SoCs, to pass on the SoC ID to the PMIC setup routine.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

We will soon make more use of the Allwinner SoC ID, to differentiate the
platform setup.
Introduce definitions to avoid dealing with magic numbers and make the
code more readable.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The SRAM in the Allwinner H6 SoC starts at 0x2000, with the last part
ending at 0x117fff (although with gaps in between).
So SUNXI_SRAM_SIZE should be 0xf8000, not 0x98000.

Fix this to map the arisc exception vector area, which we will need
shortly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

According to the documentation, platforms may choose to trade memory
footprint for performance (and elegancy) by not providing a separately
mapped coherent page.

Since a debug build is getting close to the SRAM size limit already, this
allows us to save about 3.5KB of BSS and have some room for future
enhancements.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if that is configured).

To decrease the memory footprint of ATF, we save on some page tables by
reducing the memory mapping to the actually required regions: SRAM, device
MMIO, secure DRAM and U-Boot (to be used later).
This introduces a non-identity mapping for the DRAM regions.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

For the two different platforms we support in the Allwinner port we
mostly rely on header files covering the differences. This leads to the
platform.mk files in the respective directories to be almost identical.

To avoid further divergence and make sure that one platform doesn't
break accidentally, let's create a shared allwinner-common.mk file and
include that from the platform directory.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

 - ddr
 - pfc [pin function controller]
 - qos [bandwidth]

checkpatch.pl is generating too many errors.

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date:   Thu Aug 30 21:26:41 2018 +0900
	Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
  git@github.com:ARMmbed/mbedtls.git [devel]

  Merge: 68dbc94 f34a4c1
  Author: Simon Butcher <simon.butcher@arm.com>
  Date:   Thu Aug 30 00:57:28 2018 +0100

* optee_os:
  https://github.com/BayLibre/optee_os



  Until it gets merged into OP-TEE, the port requires Renesas' Trusted
  Environment with a modification to support power management.

  Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  Date:   Thu Aug 30 16:49:49 2018 +0200
    plat-rcar: cpu-suspend: handle the power level
Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
  The port has beent tested using mainline uboot.

  Author: Fabio Estevam <festevam@gmail.com>
  Date:   Tue Sep 4 10:23:12 2018 -0300

*linux:
  The port has beent tested using mainline kernel.

  Author: Linus Torvalds <torvalds@linux-foundation.org>
  Date:   Sun Sep 16 11:52:37 2018 -0700
      Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to  BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware


Tests
-----

* cpuidle
  -------
   enable kernel's cpuidle arm_idle driver and boot

* system suspend
  --------------
  $ cat suspend.sh
    #!/bin/bash
    i2cset -f -y 7 0x30 0x20 0x0F
    read -p "Switch off SW23 and press return " foo
    echo mem > /sys/power/state

* cpu hotplug:
  ------------
  $ cat offline.sh
    #!/bin/bash
    nbr=$1
    echo 0 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

  $ cat online.sh
    #!/bin/bash
    nbr=$1
    echo 1 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline
Signed-off-by: ldts <jramirez@baylibre.com>

Leave the caches on and explicitly flush any data that
may be stale when the core is powered down. This prevents
non-coherent interconnect access which has negative side-
effects on AM65x.
Signed-off-by: Andrew F. Davis <afd@ti.com>

When HW_ASSISTED_COHERENCY is enabled we can use spinlocks
instead of using the more complex and slower bakery algorithm.

Change-Id: I9d791a70050d599241169b9160a67e57d5506564
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

macro jump_if_cpu_midr is used commonly by many arm platform.
It has now been relocated to common place to remove duplication
of code.

Change-Id: Ic0876097dbc085df4f90eadb4b7687dde7c726da
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

Signed-off-by: Yann Gautier <yann.gautier@st.com>

This driver is for the STMicroelectronics sdmmc2 IP
which is in STM32MP1 SoC.
It uses the MMC framework, and can address either eMMC or SD-card.
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Change-Id: Ica944acc474a099219d50b041cfaeabd4f3d362f
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

This file is shared between FVP and all CSS platforms. While it may be
true that some definitions can be common, it doesn't make sense
conceptually. For example, the stack size depends on the platform and so
does the SRAM size.

After removing them, there are not enough common definitions to justify
having this header, so the other definitions have been moved to the
platform_def.h of FVP, board_css_def.h and arm_def.h.

Change-Id: Ifbf4b017227f9dfefa1a430f67d7d6baae6a4ba1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This file is only used by Juno as all other CSS platforms have their own
private memory maps.

Change-Id: I1c9f27aac7b1d8bff4d92674e8bde5505b93c8c4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is
meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix
has been removed from wherever it was used as "S-EL3".

Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

In the function, bl1_early_platform_setup in the file
plat/arm/css/sgm/sgm_bl1_setup.c:

  plat_config_init();

  arm_bl1_early_platform_setup();

The debug messages logged by plat_config_init() are lost because
the console is initialized in the function
arm_bl1_early_platform_setup()

To see the logs of plat_config_init, this fix re-orders above calls
so that the console is initialized before call to plat_config_init.

Change-Id: I2e98f1f67c591cca24e28905acd0838ea3697a7c
Signed-off-by: Girish Pathak <girish.pathak@arm.com>

This way it can be reused by other platforms if needed.

Note that this driver is designed to work with the Versatile Express NOR
flash of Juno and FVP. In said platforms, the memory is organized as an
interleaved memory of two chips with a 16 bit word.

Any platform that wishes to reuse it with a different configuration will
need to modify the driver so that it is more generic.

Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This lets any future CSS platforms to use RESET_TO_BL31 flag.

Change-Id: I32a90fce43cb0c6f4d33589653a0fd6a7ecc9577
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

Change-Id: Ia00eba2b18804e6498d935d33ec104953e0e5e03
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

Before switching to new API the scp_bl2 handler was invoked from
bl2/bl2_image_load.c which was removed. Invoke the platform specific
scp_bl2 handler in analogy to ARM and HiSilicon.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

The BLE is the pre-TF-A boot stage required by Marvell Armada
BootROM for bringing up DRAM and allow the boot image copy to it.
Since this is not a standard boot level and only uses the TF-A
as a build environment, it was introduced out of source tree.
However it turns out that such remote location introduces additional
complexity to the upstream TF-A build process.
In order to simplify the build environment the BLE source folder
is relocated from the external repository to A8K platform directory.
The build documentation is updated accordingly.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Map the initialization code for BL31 to overlap with the memory
required for the secondary cores stack. Once BL31 has been
initialized the memory can be remapped to RW data so that it can
be used for secondary cores stacks. By moving code from .text to
.text.init the size of the BL31 image is decreased by a page.

Split arm_common.ld.S into two linker scripts, one for tzc_dram
(arm_tzc_dram.ld.S) and one for reclaiming initialization code
(arm_reclaim_init.ld.S) so that platforms can chose which memory
regions they wish to include.

Change-Id: I648e88f3eda1aa71765744cf34343ecda9320b32
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

Mark the GICv3, CCI and CCN code only used in Bl31 initialization
with __init to be reclaimed once no longer needed.

Change-Id: I3d77f36758450d9d1d87ecc60bc1c63fe4082667
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

Mark the initialization functions found in the BL31 boot sequence
as __init so they can be reclaimed when no longer needed.

Change-Id: I687a89346419c7710ef5097feaa325d83c527697
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

Remove ARM_MAP_BL_ROMLIB memory region macro as it is now split
into two regions for code and data

Change-Id: Ic17b5b584933c196db29fe83051d7e0a8e92911c
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

- Fix build issue
- Add initial memory parameters descriptors for BL2
- Migrate to image load V2

Basic build and run test passed on MacchiatoBin board.
Need to fix the service CPU (CM3) image load procesure and test
OPTEE functionality, which probably will require additional work.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>