- 20 Jan, 2020 12 commits
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Lionel Debieve authored
STM32MP1 platform is able to boot from raw NAND devices. These modifications add this support using the new raw NAND framework. Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Add fmc2_nand driver support. The driver implements only read interface for NAND devices. Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Nicolas Le Bayon authored
For STM32MP1, the address space is 4GB, which can be first divided in 4 parts of 1GB. This LVL1 table is already mapped regardless of MAX_XLAT_TABLES. Fixing typo: Replace Ko to KB. BL2/sp_min for platform STM32MP1 requires 4 MMU translation tables: - a level2 table and a level3 table for identity mapped SYSRAM - a level2 table mapping 2MB of BootROM runtime resources - a level2 table mapping 2MB of secure DDR (case BL32 is OP-TEE) Change-Id: If80cbd4fccc7689b39dd540d6649b1313557f326 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Device size could be more than 4GB, we must define size as unsigned long long. Change-Id: I52055cf5c1c15ff18ab9e157aa9b73c8b4fb7b63 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Add a new entry to find register properties by name and include new assert functions to limit address cells to 1 and size cells to 1. Change-Id: Ide59a795a05fb2af36bd07fec15e5a3adf196226 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Nicolas Le Bayon authored
Adds compilation flags to specify which drivers will be embedded in the generated firmware. Change-Id: Ie9decc89c3f26cf17e7148a3a4cf337fd35940f7 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Add the standard CLAMP macro. It ensures that x is between the limits set by low and high. If low is greater than high the result is undefined. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Ia173bb9ca51bc8d9a8ec573bbc15636a94f881f4
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Lionel Debieve authored
Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __popcountsi2(si_int a) and __popcountdi2(di_int a) builtin which are required by a driver that uses a __builtin_popcount(). Change-Id: I8e0d97cebdd90d224690c8ce1b02e657acdddb25 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
SPI-NOR framework is based on SPI-MEM framework using spi_mem_op execution interface. It implements read functions and allows NOR configuration up to quad mode. Default management is 1 data line but it can be overridden by platform. It also includes specific quad mode configuration for Spansion, Micron and Macronix memories. Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
This framework supports SPI-NAND and is based on the SPI-MEM framework for SPI operations. It uses a common high level access using the io_mtd. It is limited to the read functionalities. Default behavior is the basic one data line operation but it could be overridden by platform. Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
This framework supports SPI operations using a common spi_mem_op structure: - command - addr - dummy - data The framework manages SPI bus configuration: - speed - bus width (Up to quad mode) - chip select Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
The raw NAND framework supports SLC NAND devices. It introduces a new high level interface (io_mtd) that defines operations a driver can register to the NAND framework. This interface will fill in the io_mtd device specification: - device_size - erase_size that could be used by the io_storage interface. NAND core source file integrates the standard read loop that performs NAND device read operations using a skip bad block strategy. A platform buffer must be defined in case of unaligned data. This buffer must fit to the maximum device page size defined by PLATFORM_MTD_MAX_PAGE_SIZE. The raw_nand.c source file embeds the specific NAND operations to read data. The read command is a raw page read without any ECC correction. This can be overridden by a low level driver. No generic support for write or erase command or software ECC correction. NAND ONFI detection is available and can be enabled using NAND_ONFI_DETECT=1. For non-ONFI NAND management, platform can define required information. Change-Id: Id80e9864456cf47f02b74938cf25d99261da8e82 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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- 17 Jan, 2020 4 commits
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Soby Mathew authored
* changes: io: change seek offset to signed long long compiler_rt: Import aeabi_ldivmode.S file and dependencies
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Mark Dykes authored
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Mark Dykes authored
* changes: zynqmp: pm: clock: Move custom flags to typeflags zynqmp: pm: clock: Add support for custom type flags plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list
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Manish Pandey authored
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- 16 Jan, 2020 1 commit
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Mark Dykes authored
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- 15 Jan, 2020 13 commits
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Manish Pandey authored
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Manish Pandey authored
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Tien Hock, Loh authored
UEFI decompression will fail if the payload size is too large and the load address is too low. This patch moves the payload to a higher address to fix the issue Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396
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Hadi Asyrafi authored
All function in socfpga_sip_svc.c should only be called locally except sip_smc_handler(). Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib84ef9a2e521967baa4cfd32e6bc569dd3a5d2f5
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Manish Pandey authored
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Alexei Fedorov authored
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Samuel Holland authored
Now that there is plenty of space (32 KiB) available for NOBITS sections, we can afford using an entire page for coherent memory. In fact, because it simplifies the code, this is a beneficial change for loaded image (.text) size, where we are still close to the size limit. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9
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Luka Kovacic authored
Implements a way to add platform specific power off code to a Marvell Armada 8K platform. Marvell Armada 8K boards can now add a board/system_power.c file that contains a system_power_off() function. This function can now send a command to a power management MCU or other board periferals before shutting the board down. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: Iaba20bc2f603195679c54ad12c0c18962dd8e3db --- I am working on a device that will be ported later, which has a custom power management MCU that handles LEDs, board power and fans and requires this separation.
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Marek Vasut authored
Add missing #address-cells and #size-cells into generated DT, otherwise the DT is invalid. While the parsers thus far handled this correctly via various fallbacks, this is not applicable in the long run, so fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ic808a3b27b93e5258ec1a19acc3d593e53625c15
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Ravi Patel authored
Existing implementation does not allow to change the value of the DIV1 because DIV2 does not have SET_RATE_PARENT flag. This causes DIV1 value to be fixed and only value of DIV2 will be adjusted according to required clock rate. Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b
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Rajan Vaja authored
Linux expects custom flags in type flags. So move custom flags to type flags instead of providing them to clock core flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78
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Rajan Vaja authored
Add support to add extra custom type flags and provide to caller in topology query. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40
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Rajan Vaja authored
Add GET_CALLBACK_DATA function again as now Linux driver supports both mailbox as well as ISR method. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ieb99d61976e1cb718fcd1021d9cf4958e7556c81
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- 14 Jan, 2020 9 commits
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Manish Pandey authored
* changes: intel: Implement platform specific system reset 2 intel: Enable SiP SMC secure register access
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Manish Pandey authored
Merge "uniphier: call uniphier_scp_is_running() only when on-chip STM is supported" into integration
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Manish Pandey authored
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Olivier Deprez authored
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Jan Kiszka authored
It's in fact mandatory. Seen with RPi firmware 1.20190925. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Change-Id: I80739b74f25817294adc52cfd26a3ec59c06f892
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Manish Pandey authored
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Manish Pandey authored
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Sandrine Bailleux authored
* changes: zynqmp: pm: Add LPD WDT clock to the pm_clock structure zynqmp: pm: Fix clock models and IDs of GEM-related clocks zynqmp: pm: Rename FPD WDT clock ID plat: xilinx: zynqmp: Correct syscnt freq for QEMU arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR arm64: zynqmp: Add id for new RFSoC device ZU39DR
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Alexei Fedorov authored
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- 13 Jan, 2020 1 commit
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Sandrine Bailleux authored
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