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Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b

Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78

Add support to add extra custom type flags and provide
to caller in topology query.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40

Add GET_CALLBACK_DATA function again as now Linux driver
supports both mailbox as well as ISR method.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ieb99d61976e1cb718fcd1021d9cf4958e7556c81

CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid
clock list would not be registered to CCF framework and so
cannot be used as parent of other clocks.

WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock).
If CLK_TOPSW_LSBUS is not registered, CCF would not recognize
that clock and hence rate of WDT clock would be calculated to
be 0 by CCF(as parent rate is considered 0).

So it is necessary to allow registration of CLK_TOPSW_LSBUS
clock.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iceaba0f137784fc5fd666e66ffc4c143381c6ccc

This patch adds LPD WDT clock node to the pm_clock clocks structure list
so that LPD WDT can be used from Linux.

Also this patch removes the CLK_LPD_LSBUS from invalid clock list to
allow the registration of this clock to CCF framework as it is the
parent of LPD WDT.
Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403

GEM-related clock models were incorrect and are fixed as follows
(documented below for GEM0, but the same holds for any GEM ID):

- CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and
 the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this
 clock is newly introduced in this patch.

- CLK_GEM0_REF models the clock mux that selects the reference clock
 for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This
 mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL.
 Note that the routing of external clock to the mux is not modelled
 and is assumed to be configured by the FSBL if required, and not
 changeable at runtime. The ID of this clock is introduced in this patch.

- CLK_GEM0_TX models clock with only a gate that is controlled via
 bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is
 CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID
 value of CLK_GEM0_REF. This is done in order to fix the clock models
 and incorrect binding without requiring to change device-tree (binding
 of clock IDs to GEM interface).

- CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT
 bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced
 from external RGMII PHY (via MIO or EMIO). We do not model the whole
 clock path to the Rx gate, since this is configured by the FSBL and
 never changed at runtime (and there is no mechanism to change the
 path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the
 previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX
 were swapped in device tree, so by fixing the IDs this way there is no
 need for device tree fix.

Rates of the external RX/TX clocks can be specified in device tree if
needed. Right now, that's not necessary because Tx clock is sourced
from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas
the Rx clock is sourced from external reference and the driver never
attempts to get/get clock rate (only to enable it). If this changes in
future, ATF clock model doesn't need to be changed. Instead, the clock
rates for gem0_tx_ext and gem0_rx_ext have to be specified in device
tree.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <will.wong@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79

This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT.
Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I4d00a59b1dc54920115a2da55e8a06347fe2231c

Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie0137feb9b7e24ed4e5d6cbf81c58ac77bb69214

Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b
and 0x7e.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I2978f16bb663853951ef8059bf0327f909447f34

This patch adds new RFSoC device ZU39DR to zynqmp
devices list
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35735da9e7d7facbde44323c49eac1b714e4909d

The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.

The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
  processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
  L2 accesses
- manage ACP accesses.

Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.

This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT

Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ia2f69e26e34462e113bc2cad4dcb923e20b8fb95

Some platforms are extremely memory constrained and must split BL31
between multiple non-contiguous areas in SRAM. Allow the NOBITS
sections (.bss, stacks, page tables, and coherent memory) to be placed
in a separate region of RAM from the loaded firmware image.

Because the NOBITS region may be at a lower address than the rest of
BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this
region, or el3_entrypoint_common would attempt to invalidate the dcache
for the entire address space. New symbols __NOBITS_{START,END}__ are
added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the
NOBITS region is invalidated separately.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idedfec5e4dbee77e94f2fdd356e6ae6f4dc79d37

All the SoCs in 64-bit UniPhier SoC family support EL2.

Just hard-code MODE_EL2 instead of using el_implemented() helper.

Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

spm resume will restore Vmodem/Vcore voltages
back based on the SPM_DVS_LEVEL.

Change-Id: I37ff7ce4ba62219c1858acea816c5bc9ce6c493e
Signed-off-by: Roger Lu <roger.lu@mediatek.com>

Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.

Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Add additional field definitions for
Cortex_A72 L2 Control registers

Change-Id: I5ef3a6db41cd7c5d9904172720682716276b7889
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

* changes:
  spm-mm: Rename aarch64 assembly files
  spm-mm: Rename source files
  spm-mm: Rename spm_shim_private.h
  spm-mm: Rename spm_private.h
  spm-mm: Rename component makefile
  spm-mm: Remove mm_svc.h header
  spm-mm: Refactor spm_svc.h and its contents
  spm-mm: Refactor secure_partition.h and its contents
  spm: Remove SPM Alpha 1 prototype and support files
  Remove dependency between SPM_MM and ENABLE_SPM build flags

Change-Id: I2bab67f319758dd033aa689d985227cad796cdea
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Change-Id: I851be04fc5de8a95ea11270996f8ca33f0fccadb
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Change-Id: I575188885ebed8c5f0682ac6e0e7dd159155727f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Change-Id: Ie47009158032c2e8f35febd7bf5458156f334ead
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Change-Id: Idcd2a35cd2b30d77a7ca031f7e0172814bdb8cab
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

The contents of this header have been merged into the spm_mm_svc.h
header file.

Change-Id: I01530b2e4ec1b4c091ce339758025e2216e740a4
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Change-Id: I91c192924433226b54d33e57d56d146c1c6df81b
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Before adding any new SPM-related components we should first do
some cleanup around the existing SPM-MM implementation. The aim
is to make sure that any SPM-MM components have names that clearly
indicate that they are MM-related. Otherwise, when adding new SPM
code, it could quickly become confusing as it would be unclear to
which component the code belongs.

The secure_partition.h header is a clear example of this, as the
name is generic so it could easily apply to any SPM-related code,
when it is in fact SPM-MM specific.

This patch renames the file and the two structures defined within
it, and then modifies any references in files that use the header.

Change-Id: I44bd95fab774c358178b3e81262a16da500fda26
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component that, in turn, enables partition managers
at S-EL2 / S-EL1.

This patch removes:

- The core service files (std_svc/spm)
- The Resource Descriptor headers (include/services)
- SPRT protocol support and service definitions
- SPCI protocol support and service definitions

Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>

There are two different implementations of Secure Partition
management in TF-A. One is based on the "Management Mode" (MM)
design, the other is based on the Secure Partition Client Interface
(SPCI) specification. Currently there is a dependency between their
build flags that shouldn't exist, making further development
harder than it should be. This patch removes that
dependency, making the two flags function independently.

Before: ENABLE_SPM=1 is required for using either implementation.
        By default, the SPCI-based implementation is enabled and
        this is overridden if SPM_MM=1.

After: ENABLE_SPM=1 enables the SPCI-based implementation.
       SPM_MM=1 enables the MM-based implementation.
       The two build flags are mutually exclusive.

Note that the name of the ENABLE_SPM flag remains a bit
ambiguous - this will be improved in a subsequent patch. For this
patch the intention was to leave the name as-is so that it is
easier to track the changes that were made.

Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a
Signed-off-by: Paul Beesley <paul.beesley@arm.com>