- 08 Jun, 2020 1 commit
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Tien Hock Loh authored
There are additional instruction needed to enable the global timer. This fixes the global timer initialization Signed-off-by:Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98
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- 01 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from agilex and stratix10 Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
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- 17 Jul, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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- 04 Feb, 2019 1 commit
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Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by:
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