- 08 Apr, 2021 1 commit
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Yann Gautier authored
Create a dedicated static struct mmc_device_info mmc_info mmc_info instead of having this in stack. A boot issue has been seen on some platform when applying patch [1]. [1] 13f3c516 ("mmc:prevent accessing to the released space in case of wrong usage") Signed-off-by:
Yann Gautier <yann.gautier@foss.st.com> Change-Id: Id52c0be61a30f453a551385883eaf3cbe32b04b9
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- 27 Oct, 2020 1 commit
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Chee Hong Ang authored
For each count down of time out counter, wait for number of miliseconds to ensure the time out duration is predictive. Signed-off-by:Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b
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- 24 Oct, 2020 1 commit
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Chee Hong Ang authored
Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by:
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- 19 Aug, 2020 1 commit
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch update each Intel's platform makefiles to include GICv2 makefile instead of manually sourcing individual c files. This aligns with latest changes from commit #1322dc94 . Signed-off-by:
Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib1f446a6fc578f73a9ef86f9708ddf12d7d75f48
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- 25 Feb, 2020 2 commits
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by:Andre Przywara <andre.przywara@arm.com>
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Tien Hock, Loh authored
This initializes the EMAC PHY in both Stratix 10 and Agilex, without this, EMAC PHY wouldn't work correctly. Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6 Signed-off-by:
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- 05 Feb, 2020 1 commit
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Hadi Asyrafi authored
Introduce support for RSU that can be initiated through SMC calls. Added features as below: - RSU status - RSU update - RSU HPS notify - RSU get sub-partition Signed-off-by:
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- 03 Feb, 2020 1 commit
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Hadi Asyrafi authored
Platform handoff structure no longer includes boot source selection. Hence, those settings can now be configured through socfpga_plat_def.h. Signed-off-by:
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- 16 Jan, 2020 6 commits
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Hadi Asyrafi authored
Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: -
Hadi Asyrafi authored
This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by: -
Hadi Asyrafi authored
Refactored system manager driver to be shared across both intel platform Signed-off-by: -
Hadi Asyrafi authored
Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: -
Hadi Asyrafi authored
Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: -
Hadi Asyrafi authored
Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by:
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- 09 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by:Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 30 Dec, 2019 1 commit
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Hadi Asyrafi authored
Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by:
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- 17 Dec, 2019 2 commits
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Hadi Asyrafi authored
Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL Signed-off-by: -
Hadi Asyrafi authored
This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by:
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- 12 Dec, 2019 1 commit
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Hadi Asyrafi authored
remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by:
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- 28 Nov, 2019 5 commits
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Hadi Asyrafi authored
Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: -
Hadi Asyrafi authored
Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: -
Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: -
Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 13 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by:
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- 07 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by:
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- 02 Aug, 2019 1 commit
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Hadi Asyrafi authored
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by:
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- 01 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from agilex and stratix10 Signed-off-by:
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- 11 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by:Justin Chadwell <justin.chadwell@arm.com>
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- 10 Jul, 2019 1 commit
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Tien Hock, Loh authored
MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by:Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a
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- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by:Ambroise Vincent <ambroise.vincent@arm.com>
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- 26 Jun, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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- 21 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Watchdog driver support & enablement during platform setup Signed-off-by:
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- 13 Mar, 2019 2 commits
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Muhammad Hadi Asyrafi Abdul Halim authored
Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: -
Muhammad Hadi Asyrafi Abdul Halim authored
To support the enablement of QSPI booting Signed-off-by:
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- 08 Mar, 2019 2 commits
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Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: -
Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by:
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- 07 Mar, 2019 2 commits
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Muhammad Hadi Asyrafi Abdul Halim authored
Change map region for device 2 from non-secure to secure Signed-off-by: -
Tien Hock, Loh authored
We should be using zeromem to scrub memory instead of memset. This would improve the performance by 200x Signed-off-by:
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- 26 Feb, 2019 1 commit
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Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by:
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