- 26 Jul, 2018 7 commits
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Sughosh Ganu authored
Add platform specific changes needed to add support for the RAS feature on SGI575 platform, including adding a mapping for the CPER buffer being used on SGI575 platform. Change-Id: I01a982e283609b5c48661307906346fa2738a43b Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
Add a platform specific handler for RAS interrupts and configure the platform RAS interrupts for EL3 handling. The interrupt handler passes control to StandaloneMM code executing in S-EL0, which populates the CPER buffer with relevant error information. The handler subsequently invokes the SDEI client which processes the information in the error information in the CPER buffer. The helper functions plat_sgi_get_ras_ev_map and plat_sgi_get_ras_ev_map_size would be defined for sgi platforms in the subsequent patch, which adds sgi575 specific RAS changes. Change-Id: I490f16c15d9917ac40bdc0441659b92380108d63 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
The secure partition manager reserves chunks of memory which are used for the S-EL0 StandaloneMM image and the buffers required for communication between the Non-Secure world with the StandaloneMM image. Add the memory chunks to relevant arrays for mapping the regions of memory with corresponding attributes. Change-Id: If371d1afee0a50ca7cacd55e16aeaca949d5062b Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
The SGI platforms need to allocate memory for CPER buffers. These platform buffers would be placed between the shared reserved memory and the per cpu stack memory, thus the need to redefine stack base pointer for these platforms. This patch allows each board in ARM platform to define the PLAT_SP_IMAGE_STACK_BASE. Change-Id: Ib5465448b860ab7ab0f645f7cb278a67acce7be9 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
Include arm_spm_def.h in the platform_def.h file. Without this inclusion, we get build errors like In file included from services/std_svc/spm/sp_setup.c:12:0: services/std_svc/spm/sp_setup.c: In function 'spm_sp_setup': services/std_svc/spm/sp_setup.c:61:57: error: 'PLAT_SPM_BUF_BASE' undeclared (first use in this function) write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE); Now that the platform_def.h includes arm_spm_def.h, remove inclusion of platform_def.h in arm_spm_def.h to remove the circular dependency. Change-Id: I5225c8ca33fd8d288849524395e436c3d56daf17 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
Add a null pointer check for the error record probe function -- avoids a panic in case a platform has not defined it. Change-Id: I1139fa0df33297a12ec16615cacd07540925f991 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
The board_arm_def.h header file needs to be included via the platform definition header. Not doing so, results in a redefinition error of PLAT_ARM_MAX_BL31_SIZE macro, if defined in the platform definition file. Change-Id: I1d178f6e8a6a41461e7fbcab9f6813a2faa2d82b Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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- 25 Jul, 2018 5 commits
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danh-arm authored
Fix several MISRA defects in PSCI library
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danh-arm authored
Add STMicroelectronics STM32MP1 platform support
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danh-arm authored
Reword LOAD_IMAGE_V2 in user guide & fix a typo
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danh-arm authored
Arm platforms: Fix type mismatch for arm_pm_idle_states
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danh-arm authored
Rework page table setup for varying number of mem regions
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- 24 Jul, 2018 26 commits
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
platform.mk is updated to have compilation rules for DTB, stm32image tool, and the concatenation of the 3 binaries. A new linker script and an assembly file are added to manage this. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
This tools adds a specific header to ST TF-A binary. This header is used by STM32MP1 ROM code to check the bootloader. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
Those device tree files are taken from STM32MP1 U-Boot and Linux. And they are updated to fit TF-A needs. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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Yann Gautier authored
The DDR driver is under dual license, BSD and GPLv2. The configuration parameters are taken from device tree. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
If a PMIC companion chip is present on board, it has to be configured for regulators supplies. This check is done with board DT configuration. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com>
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
This will be used by BL33 to get boot device and instance. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
The management of pinctrl nodes of device tree is also added. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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Yann Gautier authored
The clock driver is under dual license, BSD and GPLv2. The clock driver uses device tree, so a minimal support for this is added. The required files for driver and DTS files are in include/dt-bindings/. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
STM32MP1 is a microprocessor designed by STMicroelectronics, based on a dual Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A. STM32MP1 uses BL2 compiled with BL2_AT_EL3. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com>
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Daniel Boulby authored
Change arm_setup_page_tables() to take a variable number of memory regions. Remove coherent memory region from BL1, BL2 and BL2U as their coherent memory region doesn't contain anything and therefore has a size of 0. Add check to ensure this doesn't change without us knowing. Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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danh-arm authored
synquacer: Enable optional OP-TEE support
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danh-arm authored
Double-fault and fatal error handling support
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John Tsichritzis authored
Change-Id: Id2639218dfffec84d8b0fa295d7e896129d4fcd7 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Sumit Garg authored
OP-TEE loading is optional on Developerbox controlled via SCP firmware. To check if OP-TEE is loaded or not, we use DRAM1 region info passed by SCP firmware. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
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danh-arm authored
hikey: include TBB in BL1
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Jeenu Viswambharan authored
This also gets rid of MISRA violations for Rule 8.3 and 8.4. Change-Id: I45bba011b16f90953dd4b260fcd58381f978eedc Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Antonio Nino Diaz authored
MISRA C-2012 Rules 10.1, 10.3, 17.8 and 20.7. Change-Id: I3980bd2a1d845559af4bbe2887a0250d0506a064 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
MISRA C-2012 Rules 10.1, 10.3 and 20.7. Change-Id: I972ce63f0d8fa157ed17e826b84f218fe498c517 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
MISRA C-2012 Rules 10.1 and 10.3. Change-Id: I88cd5f56cda5780f2e0ba541c0f5b561309ab3af Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix violations of MISRA C-2012 Rules 8.13, 10.1, 10.3, 17.7 and 20.7. Change-Id: I6f45a1069b742aebf9e1d6a403717b1522083f51 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix violations of MISRA C-2012 Rules 10.1, 10.3, 13.3, 14.4, 17.7 and 17.8. Change-Id: I6c9725e428b5752f1d80684ec29cb6c52a5c0c2d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Jul, 2018 1 commit
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Haojian Zhuang authored
BL1 is used in recovery mode on HiKey. The TBB implementation on HiKey is in BL2. It means that user need to build ATF BL2 with TBB and ATF BL1 with non-TBB. It's inconvenient. So include TBB in BL1, too. Signed-off-by: Teddy Reed <teddy@prosauce.org> Signed-off-by: Victor Chong <victor.chong@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 20 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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