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  1. 01 Apr, 2019 2 commits
  3. 26 Mar, 2019 1 commit
  5. 21 Mar, 2019 2 commits
  7. 14 Mar, 2019 4 commits
    • Heiko Stuebner's avatar
      rockchip: add an fdt parsing stub for platform param · 7029e806
      Heiko Stuebner authored 
      

The Rockchip ATF platform can be entered from both Coreboot and U-Boot.
While Coreboot does submit the list of linked parameter structs as
platform param, upstream u-boot actually always provides a pointer
to a devicetree as parameter.
This results in current ATF not running at all when started from U-Boot.

To fix this, add a stub that checks if the parameter is a fdt so we
can at least boot and not get stuck. Later on we can extend this with
actual parsing of information from the devicetree.
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
      7029e806
    • Louis Mayencourt's avatar
      fvp: Increase the size of the stack for FVP · 01aa5247
      Louis Mayencourt authored 
      

When RECLAIM_INIT_CODE is 1, the stack is used to contain the .text.init
section. This is by default enable on FVP. Due to the size increase of
the .text.init section, the stack had to be adjusted contain it.

Change-Id: Ia392341970fb86c0426cf2229b1a7295453e2e32
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
      01aa5247
    • Sandrine Bailleux's avatar
      Put Pointer Authentication key value in BSS section · 47102b35
      Sandrine Bailleux authored 
      

The dummy implementation of the plat_init_apiakey() platform API uses
an internal 128-bit buffer to store the initial key value used for
Pointer Authentication support.

The intent - as stated in the file comments - was for this buffer to
be write-protected by the MMU. Initialization of the buffer would be
performed before enabling the MMU, thus bypassing write protection
checks.

However, the key buffer ended up into its own read-write section by
mistake due to a typo on the section name ('rodata.apiakey' instead of
'.rodata.apiakey', note the leading dot). As a result, the linker
script was not pulling it into the .rodata output section.

One way to address this issue could have been to fix the section
name. However, this approach does not work well for BL1. Being the
first image in the boot flow, it typically is sitting in real ROM
so we don't have the capacity to update the key buffer at any time.

The dummy implementation of plat_init_apiakey() provided at the moment
is just there to demonstrate the Pointer Authentication feature in
action. Proper key management and key generation would have to be a
lot more careful on a production system.

Therefore, the approach chosen here to leave the key buffer in
writable memory but move it to the BSS section. This does mean that
the key buffer could be maliciously updated for intalling unintended
keys on the warm boot path but at the feature is only at an
experimental stage right now, this is deemed acceptable.

Change-Id: I121ccf35fe7bc86c73275a4586b32d4bc14698d6
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      47102b35
    • John Tsichritzis's avatar
      Introduce preliminary support for Neoverse Zeus · a4546e80
      John Tsichritzis authored 
      

Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      a4546e80
  9. 13 Mar, 2019 5 commits
  11. 12 Mar, 2019 1 commit
  13. 08 Mar, 2019 4 commits
  15. 07 Mar, 2019 3 commits
  17. 04 Mar, 2019 1 commit
  19. 01 Mar, 2019 2 commits
    • Varun Wadekar's avatar
      Tegra: dummy support for the io_storage backend · 8d56e24b
      Varun Wadekar authored 
      

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.

The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.

Change-Id: I0421d35657823215229f84231896b84167f90548
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8d56e24b
    • Anson Huang's avatar
      imx: make sure GIC redistributor is awake before initialization · e655fefc
      Anson Huang authored 
      

GICR_WAKER.ProcessorSleep can only be set to zero when:
— GICR_WAKER.Sleep bit[0] == 0.
— GICR_WAKER.Quiescent bit[31] == 0.

On some platforms, when system reboot with GIC in sleep
mode but with power ON, such as on NXP's i.MX8QM, Linux
kernel enters suspend but could be requested to reboot,
and GIC is in sleep mode and it is inside a power domain
which is ON in this scenario, when CPU reset, the GIC
driver trys to set CORE's redistributor interface to awake,
with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]
both set, the ProcessorSleep bit[1] will never be clear
and cause system hang.

This patch makes sure GICR_WAKER.Sleep bit[0] and
GICR_WAKER.Quiescent bit[31] are both zeor before clearing
ProcessorSleep bit[1].
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      e655fefc
  21. 28 Feb, 2019 4 commits
  23. 27 Feb, 2019 4 commits
  25. 26 Feb, 2019 2 commits
  27. 22 Feb, 2019 1 commit
  29. 20 Feb, 2019 2 commits
    • Yann Gautier's avatar
      stm32mp1: add minimal support for co-processor Cortex-M4 · b053a22e
      Yann Gautier authored 
      

STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.

Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      b053a22e
    • Marek Vasut's avatar
      rcar_gen3: plat: Prevent PCIe hang during L1X config access · 0969397f
      Marek Vasut authored 
      

In case the PCIe controller receives a L1_Enter_PM DLLP, it will
disable the internal PLLs. The system software cannot predict it
and can attempt to perform device config space access across the
PCIe link while the controller is in this transitional state. If
such condition happens, the PCIe controller register access will
trigger ARM64 SError exception.

This patch adds checks for which PCIe controller is enabled,
checks whether the PCIe controller is in such a transitional
state and if so, first completes the transition and then restarts
the instruction which caused the SError.
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
      0969397f
  31. 19 Feb, 2019 2 commits
    • Usama Arif's avatar
      plat/arm: Support for Cortex A5 in FVP Versatile Express platform · 8f73663b
      Usama Arif authored 
      

Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex a5
is also included.

Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678
Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      8f73663b
    • Usama Arif's avatar
      plat/arm: Introduce FVP Versatile Express platform. · 6393c787
      Usama Arif authored 
      

This patch adds support for Versatile express FVP (Fast models).
Versatile express is a family of platforms that are based on ARM v7.
Currently this port has only been tested on Cortex A7, although it
should work with other ARM V7 cores that support LPAE, generic timers,
VFP and hardware divide. Future patches will support other
cores like Cortex A5 that dont support features like LPAE
and hardware divide. This platform is tested on and only expected to
work on single core models.

Change-Id: I10893af65b8bb64da7b3bd851cab8231718e61dd
Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      6393c787