- 20 Mar, 2017 26 commits
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Varun Wadekar authored
This patch disables the DCO operations when we turn OFF a CPU. DCO operations are still ON when a CPU enters a power down suspend state. Change-Id: I954a800209ffcc9ab43a77f04040608cbbbd9055 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch registers all the FIQ interrupt sources during platform setup. Currently we support AON and TOP watchdog timer interrupts. Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
For all APE clients (APER, APEW, APEDMAR, APEDMAW) set NO_OVERRIDE for MC_SID_CFG as ACAST/ADAST will be setup with the required SIDs ie. 0x7F & 0x1E. Original change by Nitin Kumbhar <nkumbhar@nvidia.com> Change-Id: Idec981b3537cc95dac6ec37cdaa38bc45b16d232 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch sets the Memory Controller's TXN_OVERRIDE registers for most write clients to CGID_ADR. This ensures ordering is maintained. In some cases WAW ordering problems could occur. There are different settings for Tegra version A01 v A02. Original changes by Alex Waterman <alexw@nvidia.com> Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The GPU is the real consumer of the video protected memory region and it needs to be in reset to pick up the new region. This patch checks if the GPU is in reset before we program the new video protected memory region settings. Change-Id: I44f553bfcf07b1975abad53b245954be966c8aeb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch fixes the incorrect override settings for the SCE hardware block. Original change by Pekka Pessi <ppessi@nvidia.com> Change-Id: I33db55d6004331988b52ca70157aab1409f4829f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch fixes the logic used to calculate the CPU index for storing the per-cpu wake times. We use the MIDR register to calculate the CPU index now. This allows us to store values for Denver/A57 CPUs properly. Change-Id: I9df0377afd4b92bbdaea495c0df06a9780a99d09 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch supports the TEGRA_SIP_NEW_VIDEOMEM_REGION SiP call to program new video memory carveout settings from the NS world. Change-Id: If9ed818fe71e6cb7461f225090105a4d8883b7a2 Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is an idle state while C7 is a powerdown state. The MCE block takes care of the entry/exit to/from these core power states and hence we call the corresponding MCE handler to process these requests. The NS driver passes the tentative time that the core is expected to stay in this state as part of the power_state parameter, which we store in a per-cpu array and pass it to the MCE block. Change-Id: I152acb11ab93d91fb866da2129b1795843dfa39b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch programs the Memory controller's control registers to disable non-secure accesses to the TZRAM. In case these registers are already programmed by the BL2/BL30, then the driver just bails out. Change-Id: Ia1416988050e3d067296373060c717a260499122 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds support for the newer platform handler functions. Commit I6db74b020b141048b6b8c03e1bef7ed8f72fd75b merges the upstream code which has already moved all the upstream supported platforms over to these handler functions. Change-Id: I621eff038f3c0dc1b90793edcd4dd7c71b196045 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch implements the 'prepare_system_reset' handler to issue the 'system reset' command to the MCE. Change-Id: I83d8d0b4167aac5963d640fe77d5754dc7ef05b1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch implements the CPU_OFF handler for powering down a CPU using the MCE driver. Change-Id: I8d455005d0b547cc61cc7778bfe9eb84b7e5480c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The System Counter Frequency has been updated to 31.25MHz after some experiments as the previous value was too high. Change-Id: I79986ee1c0c88700a3a2b1dbff2d3f00c0c412b9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
Tegra186 has an on-die, 320KB, "System RAM" memory. Out of the total size, 256KB are allocated for the CPU TrustZone binaries - EL3 monitor and Trusted OS. This patch changes the base address for bl31.bin to the SysRAM base address. The carveout is too small for the Trusted OS, so we relocate only the monitor binary. Change-Id: Ib4b667ff2a7a619589851338f9d0bfb02078c575 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch issues the 'System Off' ARI to power off the entire system from the 'prepare_system_off' handler. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch add code to power on/off the secondary CPUs on the Tegra186 chip. The MCE block is the actual hardware that takes care of the power on/off sequence. We pass the constructed CPU #, depending on the MIDR_IMPL field, to the MCE CPU handlers. This patch also programs the reset vector addresses to allow the CPUs to power on through the monitor and then jump to the linux world. Change-Id: Idc164586cda91c2009d66f3e09bf4464de9662db Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds the new SiP SMC calls to allow the NS world to interact with the MCE hardware block on Tegra186 chips. Change-Id: I79c6b9f76d68a87abd57a940613ec070562d2eac Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an offload engine for BPMP to do voltage related sequencing and for hardware requests to be handled in a better latency than BPMP-firmware. There are two interfaces to the MCEs - Abstract Request Interface (ARI) and the traditional NVGINDEX/NVGDATA interface. MCE supports various commands which can be used by CPUs - ARM as well as Denver, for power management and reset functionality. Since the linux kernel is the master for all these scenarios, each MCE command can be issued by a corresponding SMC. These SMCs have been moved to SiP SMC space as they are specific to the Tegra186 SoC. Change-Id: I67bee83d2289a8ab63bc5556e5744e5043803e51 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds driver for the Memory Controller (v2) in the newer Tegra SoCs. The newer hardware uses ARM's SMMU hardware instead of the proprietary block in the past. Change-Id: I78359da780dc840213b6e99954e45e34428d4fff Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch opens up the interfaces to read the chip's major/minor versions for all Tegra drivers to use. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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davidcunado-arm authored
ARM Cortex-A53 erratum 855873 workaround
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Andre Przywara authored
The NVidia Tegra 210 SoC contains Cortex-A53 CPUs which are affected by erratum 855873. Enable the workaround that TF provides to fix this erratum. Change-Id: I6cef4ac60ae745e9ce299ee22c93b9d2c4f6c5f2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
The Mediatek 8173 SoC contains Cortex-A53 CPUs which are affected by erratum 855873. Enable the workaround that TF provides to fix this erratum. Change-Id: I6e1c7822c320d81bdd46b8942d1d755883dac1f5 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
ARM erratum 855873 applies to all Cortex-A53 CPUs. The recommended workaround is to promote "data cache clean" instructions to "data cache clean and invalidate" instructions. For core revisions of r0p3 and later this can be done by setting a bit in the CPUACTLR_EL1 register, so that hardware takes care of the promotion. As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3, we set the bit in firmware. Also we dump this register upon crashing to provide more debug information. Enable the workaround for the Juno boards. Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 18 Mar, 2017 1 commit
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davidcunado-arm authored
Misc AArch32 fixes
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- 17 Mar, 2017 2 commits
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davidcunado-arm authored
Flush the GIC driver data after init
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davidcunado-arm authored
Patches for platforms with hardware-assisted coherency
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- 16 Mar, 2017 1 commit
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davidcunado-arm authored
Introduce version 2 of the translation tables library
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- 10 Mar, 2017 1 commit
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davidcunado-arm authored
Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs
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- 09 Mar, 2017 1 commit
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davidcunado-arm authored
SPD changes for Trusty and TLKD
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- 08 Mar, 2017 6 commits
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Antonio Nino Diaz authored
Modify ARM common makefile to use version 2 of the translation tables library and include the new header in C files. Simplify header dependencies related to this library to simplify the change. The following table contains information about the size increase in bytes for BL1 after applying this patch. The code has been compiled for different configurations of FVP in AArch64 mode with compiler GCC 4.9.3 20150413. The sizes have been calculated with the output of `nm` by adding the size of all regions and comparing the total size before and after the change. They are sumarized in the table below: text bss data total Release +660 -20 +88 +728 Debug +740 -20 +242 +962 Debug (LOG_LEVEL=50) +1120 -20 +317 +1417 Change-Id: I539e307f158ab71e3a8b771640001fc1bf431b29 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
TLBI instructions for EL3 won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. This errata has been enabled for Juno. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Added APIs to add and remove regions to the translation tables dynamically while the MMU is enabled. Only static regions are allowed to overlap other static ones (for backwards compatibility). A new private attribute (MT_DYNAMIC / MT_STATIC) has been added to flag each region as such. The dynamic mapping functionality can be enabled or disabled when compiling by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1 or 0. This can be done per-image. TLB maintenance code during dynamic table mapping and unmapping has also been added. Fixes ARM-software/tf-issues#310 Change-Id: I19e8992005c4292297a382824394490c5387aa3b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The printed output has been improved in two ways: - Whenever multiple invalid descriptors are found, only the first one is printed, and a line is added to inform about how many descriptors have been omitted. - At the beginning of each line there is an indication of the table level the entry belongs to. Example of the new output: `[LV3] VA:0x1000 PA:0x1000 size:0x1000 MEM-RO-S-EXEC` Change-Id: Ib6f1cd8dbd449452f09258f4108241eb11f8d445 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The files affected by this patch don't really depend on `xlat_tables.h`. By changing the included file it becomes easier to switch between the two versions of the translation tables library. Change-Id: Idae9171c490e0865cb55883b19eaf942457c4ccc Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The folder lib/xlat_tables_v2 has been created to store a new version of the translation tables library for further modifications in patches to follow. At the moment it only contains a basic implementation that supports static regions. This library allows different translation tables to be modified by using different 'contexts'. For now, the implementation defaults to the translation tables used by the current image, but it is possible to modify other tables than the ones in use. Added a new API to print debug information for the current state of the translation tables, rather than printing the information while the tables are being created. This allows subsequent debug printing of the xlat tables after they have been changed, which will be useful when dynamic regions are implemented in a patch to follow. The common definitions stored in `xlat_tables.h` header have been moved to a new file common to both versions, `xlat_tables_defs.h`. All headers related to the translation tables library have been moved to a the subfolder `xlat_tables`. Change-Id: Ia55962c33e0b781831d43a548e505206dffc5ea9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 07 Mar, 2017 2 commits
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Varun Wadekar authored
This patch enables the following erratas for the Tegra210 SoC: * Cortex-A57 ============= - A57_DISABLE_NON_TEMPORAL_HINT - ERRATA_A57_826974 - ERRATA_A57_826977 - ERRATA_A57_828024 - ERRATA_A57_829520 - ERRATA_A57_833471 * Cortex-A53 ============= - A53_DISABLE_NON_TEMPORAL_HINT - ERRATA_A53_826319 - ERRATA_A53_836870 Tegra210 uses Cortex-A57 revision: r1p1 and Cortex-A53 revision: r0p2. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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davidcunado-arm authored
fiptool: Embed a pointer to an image within the image descriptor
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