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    • Alexei Fedorov's avatar
      Plat AXG: Fix PLAT_MAX_PWR_LVL value · 47f2445a
      Alexei Fedorov authored 
      

This patch fixes AXG platform build error:
plat/amlogic/axg/axg_pm.c: In function 'axg_pwr_domain_off':
plat/amlogic/axg/axg_pm.c:124:43: error: array subscript 2
 is above array bounds of 'const plat_local_state_t[2]'
 {aka 'const unsigned char[2]'}
by changing PLAT_MAX_PWR_LVL from MPIDR_AFFLVL1 to MPIDR_AFFLVL2
in plat\amlogic\axg\include\platform_def.h.

Change-Id: I9a701e8f26231e62f844920aec5830664f3fb324
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      47f2445a
  17. 23 Dec, 2020 4 commits
    • Madhukar Pappireddy's avatar
      Merge changes I8cd2c1c9,I697711ee,I4a0ec150,I4f8064b9,Ie22cb2a3, ... into integration · c390ecd6
      Madhukar Pappireddy authored 
      * changes:
  ti: k3: Introduce lite device board support
  ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition
  ti: k3: Move USE_COHERENT_MEM only for the generic board
  ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain
  ti: k3: common: sec_proxy: Fill non-message data fields with 0x0
  ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg
  ti: k3: common: Enable A72 erratum 1319367
  ti: k3: common: Enable A53 erratum 1530924
  maintainers: Update maintainers for TI port
      c390ecd6
    • Pali Rohár's avatar
      marvell: uart: a3720: Implement console_a3700_core_flush · e63e4140
      Pali Rohár authored 
      

Implementation is simple, just wait for the TX FIFO to be empty.

Without this patch TF-A on A3720 truncate the last line:

  NOTICE:  BL31: Built : 16:1

With this patch TF-A on A3720 print correctly also the last line:

  NOTICE:  BL31: Built : 19:03:31, Dec 23 2020
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I2f2ea42beab66ba132afdb400ca7898c5419db09
      e63e4140
    • Andrew F. Davis's avatar
      ti: k3: Introduce lite device board support · 84af8956
      Andrew F. Davis authored 
      Add device support for the 'lite' K3 devices. These will use modified
device addresses and allow for fewer cores to save memory.

Note: This family of devices are characterized by a single cluster
of ARMv8 processor upto a max of 4 processors and lack of a level 3
cache.

The first generation of this family is introduced with AM642.

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Signed-off-by: default avatarAndrew F. Davis <afd@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Change-Id: I8cd2c1c9a9434646d0c72fca3162dd5bc9bd692a
      84af8956
    • Nishanth Menon's avatar
      ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition · 7f323eb2
      Nishanth Menon authored 
      There are two communication scheme that have been enabled to communicate
with Secure Proxy in TI.
a) A full fledged prioritized communication scheme, which involves upto
   5 threads from the perspective of the host software
b) A much simpler "lite" version which is just a two thread scheme
   involving just a transmit and receive thread scheme.

The (a) system is specifically useful when the SoC is massive
involving multiple processor systems and where the potential for
priority inversion is clearly a system usecase killer. However, this
comes with the baggage of significant die area for larger number of
instances of secure proxy, ring accelerator and backing memories
for queued messages. Example SoCs using this scheme would be:
AM654[1], J721E[2], J7200[3]  etc.

The (b) scheme(aka the lite scheme) is introduced on smaller SoCs
where memory and area concerns are paramount. The tradeoff of
priority loss is acceptable given the reduced number of processors
communicating with the central system controller. This brings about
a very significant area and memory usage savings while the loss of
communication priority has no demonstrable impact. Example SoC using
this scheme would be: AM642[4]

While we can detect using JTAG ID and conceptually handle things
dynamically, adding such a scheme involves a lot of unused data (cost
of ATF memory footprint), pointer lookups (performance cost) and still
due to follow on patches, does'nt negate the need for a different
build configuration. However, (a) and (b) family of SoCs share the
same scheme and addresses etc, this helps minimize our churn quite a
bit

Instead of introducing a complex data structure lookup scheme, lets
keep things simple by first introducing the pieces necessary for an
alternate communication scheme, then introduce a second platform
representing the "lite" family of K3 processors.

NOTE: This is only possible since ATF uses just two (secure) threads
for actual communication with the central system controller. This is
sufficient for the function that ATF uses.

The (a) scheme and the (b) scheme also varies w.r.t the base addresses
used, even though the memory window assigned for them have remained
consistent. We introduce the delta as part of this change as well.
This is expected to remain consistent as a standard in TI SoCs.

References:
[1] See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: https://www.ti.com/lit/pdf/spruid7

[2] See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: https://www.ti.com/lit/pdf/spruil1

[3] See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1

[4] See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Change-Id: I697711ee0e6601965015ddf950fdfdec8e759bfc
      7f323eb2