- 09 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by:Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 30 Dec, 2019 1 commit
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Hadi Asyrafi authored
Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4
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- 28 Nov, 2019 5 commits
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Hadi Asyrafi authored
Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: -
Hadi Asyrafi authored
Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: -
Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: -
Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 12 Sep, 2019 2 commits
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Hadi Asyrafi authored
Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: -
Hadi Asyrafi authored
Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by:
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- 19 Aug, 2019 2 commits
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Hadi Asyrafi authored
Driver will calculate DDR size instead of using hardcoded value Signed-off-by: -
Hadi Asyrafi authored
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by:
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- 15 Aug, 2019 1 commit
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Hadi Asyrafi authored
Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by:
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- 14 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by:
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- 07 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by:
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- 01 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from agilex and stratix10 Signed-off-by:
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- 30 Jul, 2019 1 commit
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Hadi Asyrafi authored
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by:
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- 24 Jul, 2019 1 commit
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Ambroise Vincent authored
"result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eb ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by:
Ambroise Vincent <ambroise.vincent@arm.com>
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- 17 Jul, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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