- 02 Oct, 2020 1 commit
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Jan Kiszka authored
stm32mp15_optee_defconfig has been dropped from U-Boot as it became identical to stm32mp15_trusted_defconfig. Furthermore give a hint how OP-TEE is supposed to be installed. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Change-Id: Id8f0bd84a87e3a62072dd4405aadddcdd3511213
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- 01 Oct, 2020 1 commit
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Alexei Fedorov authored
This patch migrates the mbedcrypto dependency for TF-A to mbedTLS repo v2.24.0 which is the latest release tag. The relevant documentation is updated to reflect the use of new version. Change-Id: I116f44242e8c98e856416ea871d11abd3234dac1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 29 Sep, 2020 1 commit
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Andre Przywara authored
As the Arm Ltd. FPGA port is now working for all existing images, add some documentation file. Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 28 Sep, 2020 1 commit
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Chandni Cherukuri authored
This patch adds support for Morello platform. It is an initial port which includes only BL31 support as the System Control Processor (SCP) is expected to take the role of primary bootloader. Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Anurag Koul <anurag.koul@arm.com>
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- 25 Sep, 2020 1 commit
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laurenw-arm authored
Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0. The workaround is a write sequence to several implementation defined registers based on A77 revision. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
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- 22 Sep, 2020 1 commit
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Javier Almansa Sobrino authored
Builds in Debug mode with Measured Boot enabled might run out of trusted SRAM. This patch allows to change the Log Level at which the Measured Boot driver will dump the event log, so the latter can be accessed even on Release builds if necessary, saving space on RAM. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I133689e313776cb3f231b774c26cbca4760fa120
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- 15 Sep, 2020 1 commit
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Manish Pandey authored
Change-Id: Iedaa83ed546eb2476849a8d53f6e05b847a48b23 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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- 14 Sep, 2020 1 commit
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Peng Fan authored
To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not clearing. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dacd0
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- 10 Sep, 2020 1 commit
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johpow01 authored
Neoverse N1 erratum 1868343 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. SDEN can be found here: https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
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- 03 Sep, 2020 1 commit
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Javier Almansa Sobrino authored
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I69365d4aed1160af41e291f6e4b1dd31cbd12e02
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- 31 Aug, 2020 1 commit
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Masahiro Yamada authored
I am leaving Socionext. Orphan the UniPhier platform until somebody takes the role. Change-Id: I54d3da6d49c1ccaaa475431654db578b683db88a Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 28 Aug, 2020 2 commits
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Javier Almansa Sobrino authored
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I542ec3cf1bb929a5656dda6dbad816b69837c646
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Manish V Badarkhe authored
Updated the cot-binding documentation to add 'id' property for the trusted and non-trusted nv-counters. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: If1c628c5b90fe403dd96c7cd0cd04f37288c965c
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- 26 Aug, 2020 1 commit
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Sandrine Bailleux authored
- Add some guidance about the type of information a patch author should provide to facilitate the review (and for future reference). - Make a number of implicit expectations explicit: - Every patch must compile. - All CI tests must pass. - Mention that the patch author is expected to add reviewers and explain how to choose them. - Explain the patch submission rules in terms of Gerrit labels. Also do some cosmetic changes, like adding empty lines, shuffling some paragraphs around. Change-Id: I6dac486684310b5a35aac7353e10fe5474a81ec5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 20 Aug, 2020 2 commits
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Sandrine Bailleux authored
Add a section for that in the coding guidelines. Change-Id: Ie6819c4df5889a861460eb96acf2bc9c0cfb494e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
Change-Id: I5362780db422772fd547dc8e68e459109edccdd0 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 18 Aug, 2020 2 commits
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Masahisa Kojima authored
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
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Manish V Badarkhe authored
Documented the CPU specific build macros created for AT speculative workaround. Updated the description of 'ERRATA_SPECULATIVE_AT' errata workaround option. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ie46a80d4e8183c1d5c8b153f08742a04d41a2af2
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- 17 Aug, 2020 1 commit
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Madhukar Pappireddy authored
SP804 TIMER is not platform specific, and current code base adds multiple defines to use this driver. Like FVP_USE_SP804_TIMER and FVP_VE_USE_SP804_TIMER. This patch removes platform specific build flag and adds generic flag `USE_SP804_TIMER` to be set to 1 by platform if needed. Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 14 Aug, 2020 4 commits
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Sandrine Bailleux authored
Ensuring that each file changed by a patch has the correct copyright and license information does not only apply to documentation files but to all files within the source tree. Move the guidance for copyright and license headers out of the paragraph about updating the documentation to avoid any confusion. Also do some cosmetic changes (adding empty lines, fitting in longer lines in the 80-column limit, ...) to improve the readability of the RST file. Change-Id: I241a2089ca9db70f5a9f26b7070b947674b43265 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
Change-Id: Ib4ad853ebb6e28adcf9ed14714d43799f9370343 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
Change-Id: I43e452c9993a8608b20ec029562982f5dcf8e6b2 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
We have noticed that Phabricator (the ticketing system on tf.org [1]) has far less visibility within the community than the mailing list [2]. For this reason, let's drop usage of Phabricator for anything else than bug reports. For the rest, advise contributors to start a discussion on the mailing list, where they are more likely to get feedback. [1] https://developer.trustedfirmware.org/project/board/1/ [2] https://lists.trustedfirmware.org/mailman/listinfo/tf-a Change-Id: I7d2d3d305ad0a0f8aacc2a2f25eb5ff429853a3f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 10 Aug, 2020 2 commits
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Alexei Fedorov authored
This patch fixes the bug when AMUv1 group1 counters was always assumed being implemented without checking for its presence which was causing exception otherwise. The AMU extension code was also modified as listed below: - Added detection of AMUv1 for ARMv8.6 - 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now calculated based on 'AMU_GROUP1_COUNTERS_MASK' value - Added bit fields definitions and access functions for AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers - Unification of amu.c Aarch64 and Aarch32 source files - Bug fixes and TF-A coding style compliant changes. Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Saurabh Gorecha authored
Adding support for QTI CHIP SC7180 on ATF Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Co-authored-by: Maulik Shah <mkshah@codeaurora.org>
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- 06 Aug, 2020 1 commit
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Madhukar Pappireddy authored
Change-Id: If82aaba9f2a5a74cfb5e4381f968166037a70037 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 04 Aug, 2020 1 commit
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Grant Likely authored
If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by: Grant Likely <grant.likely@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
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- 03 Aug, 2020 1 commit
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Madhukar Pappireddy authored
These broken links were found with the help of this command: $> sphinx-build -M linkcheck . build A sample broken link is reported as follows: (line 80) -local- firmware-design.rst#secure-el1-payloads-and-dispatchers Change-Id: I5dcefdd4b8040908658115647e957f6c2c5da7c2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 31 Jul, 2020 1 commit
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Nina Wu authored
- Add basic platform setup - Add mt8192 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: Ife34622105404a8227441aab939e3c55c96374e9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
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- 30 Jul, 2020 5 commits
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Olivier Deprez authored
Provide manifest and build options to boot OP-TEE as a guest S-EL1 Secure Partition on top of Hafnium in S-EL2. Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb
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Manish V Badarkhe authored
Openssl directory path is hardcoded to '/usr' in the makefile of certificate generation and firmware encryption tool using 'OPENSSL_DIR' variable. Hence changes are done to make 'OPENSSL_DIR' variable as a build option so that user can provide openssl directory path while building the certificate generation and firmware encryption tool. Also, updated the document for this newly created build option Change-Id: Ib1538370d2c59263417f5db3746d1087ee1c1339 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Grzegorz Jaszczyk authored
The purpose of rx_training had changed after last update. Currently it is not supposed to help with providing static parameters for porting layer. Instead, it aims to suit the parameters per connection. Change-Id: I2a146b71e2e20bd264c090a9a627d0b6bc56e052 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
Change-Id: I0cebbaa900aa518700f13cbf02f8a97e0c76b21c Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Konstantin Porotchkin authored
Add references to the OcteonTX2 CN913x family. Change-Id: I172a8e3d061086bf4843acad014c113c80359e01 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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- 28 Jul, 2020 1 commit
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johpow01 authored
The link to the exception handling framework page on the System Design / Firmware Design / Section 4.3 just links to itself, so I changed it to link to the exception handling framework component document. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I6711b423a789b2b3d1921671e8497fffa8ba33d1
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- 26 Jul, 2020 1 commit
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Manish V Badarkhe authored
Currently, 'SMCCC_ARCH_FEATURES' SMC call handler unconditionally returns 'SMC_OK' for 'SMCCC_ARCH_SOC_ID' function. This seems to be not correct for the platform which doesn't implement soc-id functionality i.e. functions to retrieve both soc-version and soc-revision. Hence introduced a platform function which will check whether SMCCC feature is available for the platform. Also, updated porting guide for the newly added platform function. Change-Id: I389f0ef6b0837bb24c712aa995b7176117bc7961 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 23 Jul, 2020 1 commit
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johpow01 authored
This reverts commit 11af40b6, reversing changes made to 2afcf1d4. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97
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- 22 Jul, 2020 2 commits
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Vijayenthiran Subramaniam authored
Update SGI-575, RD-E1-Edge and RD-N1-Edge FVP versions to 11.10/36 and add RD-N1-Edge-Dual to the list of supported Arm Fixed Virtual Platforms. Change-Id: I9e7e5662324eeefc80d799ca5341b5bc4dc39cbb Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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Alexei Fedorov authored
This patch adds support for Measured Boot functionality to FVP platform code. It also defines new properties in 'tpm_event_log' node to store Event Log address and it size 'tpm_event_log_sm_addr' 'tpm_event_log_addr' 'tpm_event_log_size' in 'event_log.dtsi' included in 'fvp_tsp_fw_config.dts' and 'fvp_nt_fw_config.dts'. The node and its properties are described in binding document 'docs\components\measured_boot\event_log.rst'. Change-Id: I087e1423afcb269d6cfe79c1af9c348931991292 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 21 Jul, 2020 1 commit
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Javier Almansa Sobrino authored
definitions Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I1c5cc8af34c02a6294ffc44a26152fb8984927fc
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