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  1. 24 Aug, 2020 6 commits
    • Varun Wadekar's avatar
      Tegra: smmu: add smmu_verify function · 21ec61a9
      Varun Wadekar authored 
      

The SMMU configuration can get corrupted or updated by
external clients during boot without our knowledge.

This patch introduces a "verify" function for the SMMU
driver, to check that the boot configuration settings are
intact.  Usually, this function should be called at the
end of the boot cycle.

This function only calls panic() on silicon platforms.

Change-Id: I2ab45a7f228781e71c73ba1f4ffc49353effe146
Signed-off-by: default avatarGeorge Bauernschmidt <georgeb@nvidia.com>
      21ec61a9
    • Varun Wadekar's avatar
      Tegra: TZDRAM setup from soc specific early_boot handlers · 13fed5a7
      Varun Wadekar authored 
      

TZDRAM setup is not required for all Tegra SoCs. The previous bootloader
can enable the TZDRAM fence due to architectural improvements in the
newer chips.

This patch moves the TZDRAM setup to early_boot handlers for SoCs to
handle this scenario.

Change-Id: I6481b4f848a4dadc20cb83852cd8e19a242b3a34
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      13fed5a7
    • Varun Wadekar's avatar
      Tegra: remove "platform_get_core_pos" function · f41dc86c
      Varun Wadekar authored 
      

This patch removes the deprecated 'plat_core_pos_by_mpidr' function
from the Tegra platform port.

Change-Id: I32e06cb7269e4fbfaf9ad6c26d0722201f982f9e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      f41dc86c
    • Varun Wadekar's avatar
      Tegra: print GICC registers conditionally · 7cd336ab
      Varun Wadekar authored 
      

The GICC interface exists only on the interrupt controllers following
the GICv2 specification.

This patch prints the GICC register contents from the platform's macro,
plat_crash_print_regs' only when TEGRA_GICC_BASE is defined. This
allows platforms using future versions of the GIC specification to
still use this macro.

Change-Id: Ia5762d0a1ae28c832664d69362a7776e46a22ad1
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7cd336ab
    • Varun Wadekar's avatar
      Tegra: spe: do not flush console in console_putc · 64b2a237
      Varun Wadekar authored 
      

SPE no longer requires the flush bit to be set to start transmitting
characters over the physical uart. Therefore, the flush bit is no
longer required when calling console_core_putc. However, flushing the
console still requires the flush bit.

This patch removes the flush bit from the mailbox messages in
console_core_putc to improve ACK latency.

Original change by: Mustafa Bilgen <mbilgen@nvidia.com>

Change-Id: I5b7d1f3ea69ea2ce308566dbaae222b04e4c373d
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      64b2a237
    • kalyanic's avatar
      Tegra: verify platform compatibility · fbcd053c
      kalyanic authored 
      

This patch verifies that the binary image is compatible with
chip ID of the platform.

Change-Id: I28db221b4442aa8827a092faadf32f110d7c5cb4
Signed-off-by: default avatarkalyanic <kalyanic@nvidia.com>
      fbcd053c
  3. 21 Aug, 2020 1 commit
  5. 20 Aug, 2020 2 commits
  7. 19 Aug, 2020 4 commits
    • Alexei Fedorov's avatar
      libc/memset: Implement function in assembler · e7d344de
      Alexei Fedorov authored 
      

Trace analysis of FVP_Base_AEMv8A model running in
Aarch32 mode with the build options listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
shows that when auth_signature() gets called
71.84% of CPU execution time is spent in memset() function
written in C using single byte write operations,
see lib\libc\memset.c.
This patch replaces C memset() implementation with assembler
version giving the following results:
- for Aarch32 in auth_signature() call memset() CPU time
reduced to 24.84%.
- Number of CPU instructions executed during TF-A
boot stage before start of BL33 in RELEASE builds:
----------------------------------------------
|  Arch   |     C      |  assembler |    %   |
----------------------------------------------
| Aarch32 | 2073275460 | 1487400003 | -28.25 |
| Aarch64 | 2056807158 | 1244898303 | -39.47 |
----------------------------------------------
The patch also replaces memset.c with aarch64/memset.S
in plat\nvidia\tegra\platform.mk.

Change-Id: Ifbf085a2f577a25491e2d28446ee95a4ac891597
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      e7d344de
    • Ruari Phipps's avatar
      SPM: Add third cactus partition to manifests · 9de91c75
      Ruari Phipps authored 
      

Add information about the third partition so it can be loaded into SPM
when running the tests
Signed-off-by: default avatarRuari Phipps <ruari.phipps@arm.com>
Change-Id: I5544e88df391ef294ddf6b5750d468d3e74892b1
      9de91c75
    • Jacky Bai's avatar
      plat: imx8m: Correct the imr mask reg offset · fb9212be
      Jacky Bai authored 
      

The number of gpc imr mask reg & the offset is different
on some SOC, so correct it & replace the magic number with
macro define.
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74
      fb9212be
    • Jacky Bai's avatar
      plat: imx8m: Keep A53 PLAT on in wait mode(ret) · 9eb1bb63
      Jacky Bai authored 
      

Keep A53 PLAT(SCU) power domain on in wait mode(ret).
RBC count only need to be set in PLAT OFF mode, so
change it accordingly.
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Change-Id: Ie55e25c8210d298506fc4dca7a9653583db45e0c
      9eb1bb63
  9. 18 Aug, 2020 8 commits
  11. 17 Aug, 2020 2 commits
  13. 14 Aug, 2020 5 commits
    • Yann Gautier's avatar
      stm32mp1: use newly introduced GICv2 makefile · 33c91baf
      Yann Gautier authored 
      

Include the GICv2 makefile in STM32MP1 SP_min makefile, and use
${GICV2_SOURCES} instead of taking drivers/arm/gic files directly.

Change-Id: Ibcaed5b0bd17f6d8cf200e208c11cc10cd6d2ee5
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      33c91baf
    • Ruari Phipps's avatar
      SPM: Add owner field to cactus secure partitions · ad86d35a
      Ruari Phipps authored 
      

For supporting dualroot CoT for Secure Partitions a new optional field
"owner" is introduced which will be used to sign the SP with
corresponding signing domain. To demonstrate its usage, this patch adds
owners to cactus Secure Partitions.
Signed-off-by: default avatarRuari Phipps <ruari.phipps@arm.com>
Change-Id: I7b760580355fc92edf5402cecc38c38125dc1cae
      ad86d35a
    • Manish Pandey's avatar
      plat/arm: enable support for Plat owned SPs · 990d972f
      Manish Pandey authored 
      

For Arm platforms SPs are loaded by parsing tb_fw_config.dts and
adding them to SP structure sequentially, which in-turn is appended to
loadable image list.

With recently introduced dualroot CoT for SPs where they are owned
either by SiP or by Platform. SiP owned SPs index starts at SP_PKG1_ID
and Plat owned SPs index starts at SP_PKG5_ID. As the start index of SP
depends on the owner, there should be a mechanism to parse owner of a SP
and put it at the correct index in SP structure.

This patch adds support for parsing a new optional field "owner" and
based on it put SP details(UUID & Load-address) at the correct index in
SP structure.

Change-Id: Ibd255b60d5c45023cc7fdb10971bef6626cb560b
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      990d972f
    • Jimmy Brisson's avatar
      Use true instead of 1 in while · 92069086
      Jimmy Brisson authored 
      

This resolves MISRA defects such as:

    plat/common/plat_bl1_common.c:63:[MISRA C-2012 Rule 14.4 (required)]
    The condition expression "1" does not have an essentially boolean type.

Change-Id: I679411980ad661191fbc834a44a5eca5494fd0e2
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      92069086
    • Jimmy Brisson's avatar
      Prevent colliding identifiers · d74c6b83
      Jimmy Brisson authored 
      

There was a collision between the name of the typedef in the CASSERT and
something else, so we make the name of the typedef unique to the
invocation of DEFFINE_SVC_UUID2 by appending the name that's passed into
the macro. This eliminates the following MISRA violation:

    bl1/bl1_main.c:233:[MISRA C-2012 Rule 5.6 (required)] Identifier
    "invalid_svc_uuid" is already used to represent a typedef.

This also resolves MISRA rule 5.9.

These renamings are as follows:
  * tzram -> secram. This matches the function call name as it has
  sec_mem in it's  name
  * fw_config_base -> config_base. This file does not mess with
  hw_conig, so there's little chance of confusion

Change-Id: I8734ba0956140c8e29b89d0596d10d61a6ef351e
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      d74c6b83
  15. 13 Aug, 2020 1 commit
  17. 10 Aug, 2020 2 commits
    • Alexei Fedorov's avatar
      plat/arm: Reduce size of BL31 binary · fa1fdb22
      Alexei Fedorov authored 
      

BL31 binary size is aligned to 4KB because of the
code in include\plat\arm\common\arm_reclaim_init.ld.S:
    __INIT_CODE_UNALIGNED__ = .;
    . = ALIGN(PAGE_SIZE);
    __INIT_CODE_END__ = .;
with all the zero data after the last instruction of
BL31 code to the end of the page.
This causes increase in size of BL31 binary stored in FIP
and its loading time by BL2.
This patch reduces the size of BL31 image by moving
page alignment from __INIT_CODE_END__ to __STACKS_END__
which also increases the stack size for secondary CPUs.

Change-Id: Ie2ec503fc774c22c12ec506d74fd3ef2b0b183a9
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      fa1fdb22
    • Saurabh Gorecha's avatar
      sc7180 platform support · 5bd9c17d
      Saurabh Gorecha authored 
      

Adding support for QTI CHIP SC7180 on ATF

Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82
Signed-off-by: default avatarSaurabh Gorecha <sgorecha@codeaurora.org>
Co-authored-by: default avatarMaulik Shah <mkshah@codeaurora.org>
      5bd9c17d
  19. 09 Aug, 2020 2 commits
  21. 06 Aug, 2020 1 commit
  23. 04 Aug, 2020 1 commit
    • Grant Likely's avatar
      Use abspath to dereference $BUILD_BASE · 29214e95
      Grant Likely authored 
      

If the user tries to change BUILD_BASE to put the build products outside
the build tree the compile will fail due to hard coded assumptions that
$BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE))
to rationalize to an absolute path every time and remove the relative
path assumptions.

This patch also adds documentation that BUILD_BASE can be specified by
the user.
Signed-off-by: default avatarGrant Likely <grant.likely@arm.com>
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
      29214e95
  25. 31 Jul, 2020 4 commits
  27. 30 Jul, 2020 1 commit
    • Andre Przywara's avatar
      arm_fpga: Support uploading a custom command line · fa30f73b
      Andre Przywara authored 
      

The command line for BL33 payloads is typically taken from the DTB. On
"normal" systems the bootloader will put the right version in there, but
we typically don't use one on the FPGAs.
To avoid editing (and possibly re-packaging) the DTB for every change in
the command line, try to read it from some "magic" memory location
instead. It can be easily placed there by the tool that uploads the
other payloads to the FPGA's memory. BL31 will then replace the existing
command line in the DTB with that new string.

To avoid reading garbage, check the memory location for containing a
magic value. This is conveniently chosen to be a simple ASCII string, so
it can just preceed the actual command line in a text file:
--------------------------------
CMD:console=ttyAMA0,38400n8 debug loglevel=8
--------------------------------

Change-Id: I5923a80332c9fac3b4afd1a6aaa321233d0f60da
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      fa30f73b